AWR1642BOOST: 如何查看L2内存分布

jian zhang 说：

雷达在处理ZOOMFFT的时候其雷达数据是否是存放在L2中的。

您是从哪里看到有关L2部分的内容，我看了一下datasheet Table 6-1. Master Subsystem, Cortex-R4F Memory Map 并没有看到L2部分的内存。

请问问题解决了吗？如果已经解决我会将此贴关闭。

我是把他放在DSP内存中的L2的

这两个文件是不是已经把L2分配了

文件1：c674x linker.cmd

#define L1P_CACHE_SIZE (4*1024)
#define L1D_CACHE_SIZE (16*1024)

MEMORY
{
PAGE 0:

#if (L1P_CACHE_SIZE < 0x8000)
L1PSRAM: o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
#endif
#if (L1D_CACHE_SIZE < 0x8000)
L1DSRAM: o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
#endif
L2SRAM_UMAP1: o = 0x007E0000, l = 0x00020000
L2SRAM_UMAP0: o = 0x00800000, l = 0x00020000
L3SRAM: o = 0x20000000, l = 0x000A0000
HSRAM: o = 0x21080000, l = 0x8000

/* PAGEs 1 and onwards are for overlay purposes for memory optimization.
Some examples:
1. Overlay one-time only text with uninitialized data.
2. Overlay L1PSRAM data path processing fast code and use copy tables
to page in (before entering data path) and out of L1PSRAM (when entering
sleep/low power).
*/
PAGE 1:
L3SRAM: o = 0x20000000, l = 0x000A0000
}

/* Set L1D, L1P and L2 Cache Sizes */
ti_sysbios_family_c64p_Cache_l1dSize = L1D_CACHE_SIZE;
ti_sysbios_family_c64p_Cache_l1pSize = L1P_CACHE_SIZE;
ti_sysbios_family_c64p_Cache_l2Size = 0;

SECTIONS
{
/* hard addresses forces vecs to be allocated there */
.vecs: {. = align(32); } > 0x007E0000

/* Allocate data preferentially in one UMAP and code (.text) in another,
this can improve performance due to simultaneous misses from L1P
and L1D caches to L2 SRAM, for more information see C674 Megamodule
User Guide section "Level 2 Memory Architecture".
The linker notation "X >> Y | Z" indicates section X is first allocated in Y
and allowed to overflow into Z and can be split from Y to Z.
The linker notation "X > Y | Z" indicates section X is first allocated in Y
and allowed to overflow into Z and cannot be split from Y to Z. Some sections
like bss are not allowed to be split so > notation is used for them */

.fardata: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
.const: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
.switch: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
.cio: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
.data: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
.rodata: {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1

.bss: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
.neardata: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
.stack: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
.cinit: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1
.far: {} > L2SRAM_UMAP0 | L2SRAM_UMAP1

.text: {} >> L2SRAM_UMAP1 | L2SRAM_UMAP0
}

文件2：dss_mmw_linker.cmd

/*----------------------------------------------------------------------------*/
/* Linker Settings */
--retain="*(.intvecs)"

--stack_size=0x1000
/*----------------------------------------------------------------------------*/
/* Section Configuration */
SECTIONS
{
systemHeap : {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1
.l2data : {} >> L2SRAM_UMAP0 | L2SRAM_UMAP1

/* L3SRAM has code that is overlaid with data, so data must be
marked uninitialized. Application can initialize this section
using _L3data_* symbols defined below. Code should be written carefully as
these are linker symbols (see for example e2e.ti.com/.../92002 ):

extern far uint8_t _L3data_start; // the type here does not matter
extern far uint8_t _L3data_size; // the type here does not matter

memset((void *)_symval(&_L3data_start), 0, (uint32_t) _symval(&_L3data_size));
*/
.l3data: type=NOINIT, start(_L3data_start), size(_L3data_size), load=L3SRAM PAGE 1

/* Bootloader cannot load L1DSRAM, make sure to mark as NOINIT */
.l1data : type=NOINIT, load=L1DSRAM

/* memory section defined in HSRAM */
.hsramdata : type=NOINIT, load=HSRAM

/* Currently bootloader does not allow loading in L1PSRAM because of supporting
low power. Below fast code is loaded in L3SRAM but run from L1PSRAM. The copy-in
is called during initialization phase and copy-out is not used but can be added when
supporting low-power mode (where L1 contents are not retained).

The functions listed in this section are paricularly picked because they contains haeavy calculation loops.
*/
.fastCode:
{
-ldsplib.lib (.text:DSPF_sp_fftSPxSP)
RADARDEMO_highAccuRangeProc_priv.oe674(.text:RADARDEMO_highAccuRangeProc_rangeEst)
RADARDEMO_highAccuRangeProc.oe674(.text:RADARDEMO_highAccuRangeProc_create)
RADARDEMO_highAccuRangeProc_priv.oe674(.text:RADARDEMO_highAccuRangeProc_accumulateInput)
RADARDEMO_highAccuRangeProc.oe674(.text:RADARDEMO_highAccuRangeProc_run)
dss_main.oe674 (.text:MmwDemo_dssDataPathProcessEvents)
dss_data_path.oe674 (.text:MmwDemo_interFrameProcessing)
dss_data_path.oe674 (.text:MmwDemo_processChirp)

} load=L3SRAM PAGE 0, run=L1PSRAM PAGE 0, table(_MmwDemo_fastCode_L1PSRAM_copy_table, compression=off)

/* This is auto generated by linker related to copy table above */
.ovly > L2SRAM_UMAP0 | L2SRAM_UMAP1

/* Overlay one-time/init-time (and non-critical in cycles) with L3 data,
will be erased during data path processing. Note do not put any
code that is required related to start/stop/reconfig processing

The RADARDEMO function in this section are the ones in the code base as algorithm options but never uses for TM demo.
For other signal chains that may use the functions listed below, they have to be removed from the overlay section, otherwise
the code will be overwrite at runtime by radar cude or other data buffer and will casue crash.
*/
.overlay:
{
// -llibsoc_xwr16xx.ae674 (.text:SOC_init)
dss_main.oe674 (.text:MmwDemo_dssInitTask)
dss_main.oe674 (.text:main)
dss_data_path.oe674 (.text:MmwDemo_dataPathInitEdma)

} > L3SRAM PAGE 0

}
/*----------------------------------------------------------------------------*/

jian zhang 说：

这两个文件是不是已经把L2分配了

是的，你可以查一下生成的map文件中空间是否都被占用。

dss的map文件中已经分配了，截图中是mss的。

您好，我想问一下这个map里面显示用掉的大小的单位是什么，是bit还是byte还是word？

L1是不能用户自己存放数据吗？

jian zhang 说：

这个map里面显示用掉的大小的单位是什么，是bit还是byte还是word？

十六进制要换算的。

jian zhang 说：

L1是不能用户自己存放数据吗？

应该是可以放的，没有看到限制。

L1，L2,L3的读写速度是不是逐渐变慢

是的。