We are designing an IRIG-B AM demodulation circuit. The input signal is IRIG-B AM, the amplitude is peak-to-peak 0.5V to 12V, and the modulation ratio is 6:1 to 2:1. In order to extract the time information from the IRIG-B AM signal, we need to do AD conversion. But The input signal has a very wide range of variation .How to design the front-end circuit for ADC(ADS8860).
Hi,
Thanks for the feedback! Input levels in dBm are relative. It would be helpful to have the full signal range to the ADC input in volts. For now, I will assume it is peak-to-peak 0.5V to 12V = 12V-0.5V = 11.5Vpp, as you mentioned in your first post. Please let me know if my understanding is incorrect. The 11.5Vpp input is larger than the ADS8860's 0V-5V input range, the input will need to be divided down. The use of a (for example) 10kohm equivalent resistor divider + the 600 ohms input impedance will not allow the internal sample and hold capacitor to settle within the acquisition time and would reduce the sampling rate to about ~8ksps, as shown below through use of the Analog Engineer's calculator:
As a result, the customer will need a driver amplifier to drive the ADC inputs. One such example is shown in the datasheet, figure 64. The customer can size the feedback resistors to divide down the input. Since this is an inverting gain amplifier configuration, a common-mode voltage is shown at the positive input of the amplifier to bring the input back within the positive 0V to 5V range. You can size your resistors as Rf = 1kohm and R1 = ~2.5kohm to allow the 11.5Vpp signal to become 4.6Vpp (-0.2V to -4.8V). You can add a 5V common-mode to the amplifier positive input to shift this voltage up to 0.2V to 4.8V to stay within the ADC's input range.
I did not go into much detail on how this op-amp was selected as the text describes that. I calculated what the minimum amplifier gain-bandwidth product (GBW) needed to be to drive this 1MSPS ADC. Other amplifiers of similar GBW and distortion may be used as well.
I hope this helps,
Best regards,
