Which document does your screenshot come from? Could you please send the link？ Is your question mainly related to TIDA-01022 or ADC12DJ3200AAVR? Because they belong to different sub forums
This is the link to the document JESD204B Physical Layer (PHY) https://www.ti.com/lit/ml/slap162/slap162.pdf We are currently using ADC12DJ3200 for the design, so there are some doubts regarding the layout here.
JESD Serdes routing does not need to be matched in length, only the P/N inter-pair needs to be, the internal FPGA elastic buffer will take care of the lane delay/mismatches.
I would download and study the layout on our ADC12DJ3100EVM. This will give you good guidance on how to route these serdes lanes and which layers to use.
Typically we route these on the top and/or bottom.
