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TRF3765时钟锁相环杂波问题

Other Parts Discussed in Thread: TRF3765
设计中使用TRF3765芯片作为PLL,电路板设计参考TRF3765评估板,基本上和评估板完全一样。设计: SPI配置和读取正确,配置芯片锁定在1GHz时钟上。结果:频谱仪上看1GHz时钟锁定,单在两边每隔2.5MHz都有一个频率,比1GHz幅度小个15dB左右,其中俭相频率设定的就是2.5MHz,锁定指示一直显示为低。现在就是不知如何能消除鉴相频率。请帮助解答,谢谢。