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器件型号：TMS320F28388D 主题：SysConfig 中讨论的其他器件
工具/软件：
您好、
尝试 通过 LUT4然后将 CLB_OUTPUT_XBAR 路由到 GPIO92。 我使用逐位寄存器配置来执行此操作。问题是 GPIO92保持为零。
1. 我使用的代码如下:
100MHz 的 CLB 时钟从25MHz 晶体振荡器的 AUXPLL 生成。
InitAuxPll(XTAL_OSC, AUX_IMULT, AUX_REFDIV, AUX_ODIV, AUX_DIV, SYSCTL_DCC_BASE1);
//
// Set up CMCLK to use AUXPLL as the clock source and set the
// clock divider to 1.
//
EALLOW;
ClkCfgRegs.CMCLKCTL.bit.CMCLKDIV = 0; // 0 : Divide by 1
ClkCfgRegs.CMCLKCTL.bit.CMDIVSRCSEL = 0; // 0 : AuxPLL is the source for the CM clock divider.
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0x1; /* EPWM Clock Division Select (EPWMCLKDIV): "00" - /1 of PLLSYSCLK, "01"-/2 of PLLSYSCLK(default) */
ClkCfgRegs.PERCLKDIVSEL.bit.EMIF1CLKDIV = 0x1; /* EMIF1 module Clock division select : "0" - /1 of PLLSYSCLK is selected "1"- /2 of PLLSYSCLK is selected */
ClkCfgRegs.CLKSRCCTL3.bit.XCLKOUTSEL = 0X4;
ClkCfgRegs.CLBCLKCTL.bit.CLKMODECLB2 = 0x1; /* "0" - CLB2 is synchronous to SYSCLK, 1 : CLB2 runs of asynchronous clock*/
asm(" RPT #69 || NOP"); /* Delay of 69 nop cycles ,Refer TRM */
ClkCfgRegs.CLBCLKCTL.bit.CLBCLKDIV = 0x0; /* CLB Module clock division select : "0"- /1 of AUXPLL is selected "1"- /2 of AUXPLL is selected */
asm(" RPT #69 || NOP"); /* Delay of 69 nop cycles ,Refer TRM */
ClkCfgRegs.CLBCLKCTL.bit.TILECLKDIV = 0x0; /* "0" - /1, "1" - /2*/
DevCfgRegs.CPUSEL15.bit.CLB2 = 0x0; /* "0" - CLB2 is connected to CPU1, 1 : CLB2 is connected to CPU2*/
使用 CpuSysRegs.PCLKCR17寄存器启用 CLB 时钟。
CLB2 PRESCALR 时钟作为输入信号通过本地多路复用器选择提供给逻辑块、然后提供给 LUT4。
{
EALLOW;
Clb2LogicCtrlRegs.CLB_LOCK.all = 0x5A5A0000; /* Unlock CLB1 registers*/
/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/* PRESCALER REGISTER CONTROL */
/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
Clb2LogicCtrlRegs.CLB_PRESCALE_CTRL.bit.CLKEN = 0x1; /* Enable the prescale clock/strobe generator.*/
Clb2LogicCtrlRegs.CLB_PRESCALE_CTRL.bit.STRB = 0x1; /* When set to 1, the output of the counter register bit position as selected by TAP_SELECT_VALUE will be sent out.*/
Clb2LogicCtrlRegs.CLB_PRESCALE_CTRL.bit.TAP = 0x2; /* When set to 2,0010 selects Counter Bit position 2 = 12.5MHz*/
Clb2LogicCtrlRegs.CLB_PRESCALE_CTRL.bit.PRESCALE = 0x0009; /* 10 Counts is set for generating 10MHz clock from 100MHz*/
/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/* CLB2_PRESCALE_CLK TO GPIO */
/*---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
Clb2LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.LCL_MUX_SEL_IN_0 = 31;//21; /* Connecting CLB2_PRESCALAR CLOCK as Input0 */
Clb2LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.MISC_INPUT_SEL_0 = 0;//0; /* Setting this bit to 0 will select Local Mux for Input 0 instead of MISC_INPUT*/
Clb2LogicCtrlRegs.CLB_INPUT_FILTER.bit.SYNC0 = 1; /* Synchronizer is selected for INPUT 0(which adds 2 or 3 cycles delay)*/
Clb2LogicCtrlRegs.CLB_INPUT_FILTER.bit.FIN0 = 0x0; /* No filtering*/
Clb2LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_0 = 0x0; /* Input comes from selected external input,This register Select control for Input 0 to decide between external input and CLB_GP_REG[0]*/
Clb2LogicCtrlRegs.CLB_GP_REG.bit.REG = 0x01; /* Writing a value of 1*/
Clb2LogicCtrlRegs.CLB_INPUT_FILTER.bit.PIPE0 = 0x0; /* Disabling pipelining for the input asynchronous signal*/
Clb2LogicCfgRegs.CLB_LUT4_IN0.bit.SEL_0 = 24; /* Routing the CLB2_IN0 to LUT4_IN0 through static switch block*/
Clb2LogicCfgRegs.CLB_LUT4_IN1.bit.SEL_0 = 0; /* Output low for the 2nd input of LUT4*/
Clb2LogicCfgRegs.CLB_LUT4_IN2.bit.SEL_0 = 0; /* Output low for the 3rd input of LUT4*/
Clb2LogicCfgRegs.CLB_LUT4_IN3.bit.SEL_0 = 0; /* Output low for the 4th input of LUT4*/
Clb2LogicCfgRegs.CLB_LUT4_FN1_0.bit.FN0 = 0xAAAA; /* Look up Table Output function,Output follows input*/
Clb2LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN0 = 7; /* In static switch block,LUT4_4_OUTPUT*/
Clb2LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN1 = 0; /* Input 1 is tied to 0*/
Clb2LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN2 = 0; /* Input 2 is tied to 0*/
Clb2LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.FN = 0xAA; /* Look up Table Output function,Output follows input*/
Clb2LogicCfgRegs.CLB_MISC_ACCESS_CTRL.bit.BLKEN = 0; /* "0" Writes to CLB_OUT_EN are allowed*/
Clb2LogicCtrlRegs.CLB_OUT_EN = 1<<0; /* Bit "0" is set for OUTLUT0 TO CLB2_OUT0 */
CLB2_OUT0通过 CLB_OUTPUTXBAR 连接到 GPIO92
EALLOW; ClbOutputXbarRegs.OUTPUT2MUX0TO15CFG.bit.MUX8 = 0x0; /* 00 : Select .0 input for Mux8*/ ClbOutputXbarRegs.OUTPUT2MUXENABLE.bit.MUX8 = 1; /* Respective output of Mux8 is enabled to drive the OUTPUT0 of OUTPUT-XBAR2*/ ClbOutputXbarRegs.OUTPUTLATCHENABLE.bit.OUTPUT2 = 0; /* 0: Output Latch is not selected to driven the respective output*/
问题1 -是否需要其他寄存器配置、或者是否缺少某些寄存器？
问题 2 - LUT 16位函数寄存器的工作原理是什么？
问题 3 -如何从32位 CLB_OUT_EN 寄存器中选择 CLB_OUT 信号？
