[参考译文] TMS320F28027：在 DBRED/DBFED 大于占空比的情况下使用 DB。

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https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1579681/tms320f28027-using-db-with-dbred-dbfed-larger-than-the-duty

器件型号： TMS320F28027

尊敬的专家：

我的客户使用 DB、在 PWM 中占空比较小。他们会看到以下行为：

绿色：EPWMA

蓝色：EPWMB

占空比很小、以蓝色馈送 DB 延迟并贪婪红色时、您可能会看到蓝色的高电平时间非常短、这是预期现象
现在、它们进一步降低了原始输入的占空比、因为 DBFED 和 DBRED 等于/大于占空比。他们期望蓝色的高时间会进一步减少,可能会减少到没有,然而他们看到的是如下

您能请教一下这种行为吗？

我们猜到 DB 延迟会改变边沿的顺序。例如、蓝色应首先具有上升沿、然后是下降沿、但是、上升沿会被 DB 延迟、以便下降沿到达临界点。这是可能的?

我还在这里附加了 PWM 配置：

    EALLOW;
    EPwm4Regs.TZCTL.bit.TZA = 0x02;                        //Force EPWMxA to a high state
    EPwm4Regs.TZCTL.bit.TZB = 0x02;                        //Force EPWMxB to a high state
    EPwm4Regs.TZFRC.bit.OST = 0x01;                    // Forces a one-shot trip event and sets the OSTFLG bit
    EDIS;

    EPwm4Regs.TBPRD = 750;
    EPwm4Regs.TBPHS.half.TBPHS = 0;
    EPwm4Regs.TBCTR = 0;

    
    EPwm4Regs.TBCTL.bit.CTRMODE = 0x02;            //Up-Down mode
    EPwm4Regs.TBCTL.bit.PHSEN = 0x01;                    //Sync ensable
    EPwm4Regs.TBCTL.bit.PRDLD = 0x00;                    //Shadow mode
    EPwm4Regs.TBCTL.bit.SYNCOSEL = 0x00;              //Synchronized while TBCNT=0
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0x00;                 //TBCLK = SYSCLK / (HSPCLKDIV * CLKDIV) = 100MHz/(1*1)=100MHz
    EPwm4Regs.TBCTL.bit.CLKDIV =0x00;
    EPwm4Regs.TBCTL.bit.PHSDIR = 0x00;

    EPwm4Regs.CMPA.half.CMPA = 1;
    EPwm4Regs.CMPB = 1;
    EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0x00;                  //Shadow mode
    EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0x00;                //Shadow mode
    EPwm4Regs.CMPCTL.bit.LOADAMODE = 0x02;        //Load on CTR = Zero or PRD
    EPwm4Regs.CMPCTL.bit.LOADBMODE = 0x02;        //Load on CTR = Zero or PRD
    
    EPwm4Regs.AQCTLA.bit.CAU = 0x02;                //AQ_CLEAR;        //CNT = CMPA up    ->0
    EPwm4Regs.AQCTLA.bit.CAD = 0x01;                    //AQ_SET;            //CNT = CMPB down ->1
    EPwm4Regs.AQCTLA.bit.CBU = 0x00;
    EPwm4Regs.AQCTLA.bit.CBD = 0x00;
    EPwm4Regs.AQCTLA.bit.PRD = 0x00;
    EPwm4Regs.AQCTLA.bit.ZRO = 0x00;                       
    
    EPwm4Regs.AQCTLB.bit.CAU = 0x02;            //AQ_CLEAR;            //CNT = CMPA up   ->0
    EPwm4Regs.AQCTLB.bit.CAD = 0x01;            //AQ_SET;            //CNT = CMPA down ->1
    EPwm4Regs.AQCTLB.bit.CBU = 0x00;                     
    EPwm4Regs.AQCTLB.bit.CBD = 0x00;                     
    EPwm4Regs.AQCTLB.bit.PRD = 0x00;
    EPwm4Regs.AQCTLB.bit.ZRO = 0x00;

    EPwm4Regs.AQSFRC.bit.RLDCSF = 3;                        //The active register load immediately
    EPwm4Regs.AQCSFRC.bit.CSFA = 0x01;                    //FORCE LOW
    EPwm4Regs.AQCSFRC.bit.CSFB = 0x02;                //FORCE the EPWM3B output  LOW

    EPwm4Regs.DBCTL.bit.IN_MODE =0x02;                //EPWMxA In is the source for rising-edge delayed signal.
                                                            //EPWMxB In is the source for falling-edge delayed signal.
    EPwm4Regs.DBCTL.bit.POLSEL = 0x02;                //Active high complementary (AHC). EPWMxB is inverted.
    EPwm4Regs.DBCTL.bit.OUT_MODE = 0x03;            //Enable dead band time configuration

    EPwm4Regs.DBRED = 60;                            //SYSCLK/EPWM2_DB = 60M/0.7M 
    EPwm4Regs.DBFED = 60;                            //SYSCLK/EPWM2_DB = 60M/0.7M 

    EPwm4Regs.PCCTL.bit.CHPEN = 0x00;                    //Disable chopping function

    EALLOW;
    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    EDIS;

8 个月前