[参考译文] TMS320F28055：SCI-C RX 中断不工作

// Within main.c
IER = 0x100; // Enable CPU INT   -> IER = 0x80;

// In the TX ISR
PieCtrlRegs.PIEACK.all |= 0x100; // Issue PIE ACK  -> PieCtrlRegs.PIEACK.all |= 0x80;

// In the RX ISR
PieCtrlRegs.PIEACK.all |= 0x100; // Issue PIE ack  -> PieCtrlRegs.PIEACK.all |= 0x80;

//
// Included Files
//
#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File

#define CPU_FREQ    60E6
#define LSPCLK_FREQ (CPU_FREQ/4)
#define SCI_FREQ    100E3
#define SCI_PRD     ((LSPCLK_FREQ/(SCI_FREQ*8))-1)

// Prototype statements for functions found within this file.
interrupt void scicTxFifoIsr(void);
interrupt void scicRxFifoIsr(void);
void scic_fifo_init(void);
void error(void);

// Global variables
Uint16 sdataA[2];    // Send data for SCI-C
Uint16 rdataA[2];    // Received data for SCI-C
Uint16 rdata_pointA; // Used for checking the received data
Uint16 enteredRXISR;
Uint16 enteredTXISR;

void main(void)
{
    Uint16 i;

    //
    // Step 1. Initialize System Control:
    // PLL, WatchDog, enable Peripheral Clocks
    // This example function is found in the F2805x_SysCtrl.c file.
    //
    InitSysCtrl();

    //
    // Step 2. Initialize GPIO:
    // This example function is found in the F2805x_Gpio.c file and
    // illustrates how to set the GPIO to it's default state.
    // InitGpio();
    // Setup only the GP I/O only for SCI-A and SCI-B functionality
    // This function is found in F2805x_Sci.c
    //
    InitSciGpio();

    //
    // Step 3. Clear all interrupts and initialize PIE vector table:
    // Disable CPU interrupts
    //
    DINT;

    //
    // Initialize PIE control registers to their default state.
    // The default state is all PIE interrupts disabled and flags
    // are cleared.
    // This function is found in the F2805x_PieCtrl.c file.
    //
    InitPieCtrl();

    //
    // Disable CPU interrupts and clear all CPU interrupt flags:
    //
    IER = 0x0000;
    IFR = 0x0000;

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    // This will populate the entire table, even if the interrupt
    // is not used in this example.  This is useful for debug purposes.
    // The shell ISR routines are found in F2805x_DefaultIsr.c.
    // This function is found in F2805x_PieVect.c.
    //
    InitPieVectTable();

    //
    // Interrupts that are used in this example are re-mapped to
    // ISR functions found within this file.
    //
    EALLOW;  // This is needed to write to EALLOW protected registers
    PieVectTable.SCIRXINTC = &scicRxFifoIsr;
    PieVectTable.SCITXINTC = &scicTxFifoIsr;
    EDIS;   // This is needed to disable write to EALLOW protected registers

    //
    // Step 4. Initialize all the Device Peripherals:
    //
    scic_fifo_init();  // Init SCI-C

    //
    // Step 5. User specific code, enable interrupts:
    //

    //
    // Init send data.  After each transmission this data
    // will be updated for the next transmission
    //
    for(i = 0; i<2; i++)
    {
        sdataA[i] = i;
        rdataA[i] = 0;
    }

    rdata_pointA = sdataA[0];
    enteredRXISR = 0;
    enteredTXISR = 0;

    //
    // Enable interrupts required for this example
    //
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block
    //PieCtrlRegs.PIEIER9.bit.INTx1= 1;     // PIE Group 9, INT1
    //PieCtrlRegs.PIEIER9.bit.INTx2= 1;     // PIE Group 9, INT2

    PieCtrlRegs.PIEIER8.bit.INTx5=1;   //SCI-C
    PieCtrlRegs.PIEIER8.bit.INTx6= 1;  //SCI-C

    IER = 0x80; // Enable CPU INT
    EINT;

    //
    // Step 6. IDLE loop. Just sit and loop forever (optional):
    //
    for(;;);
}

void error(void)
{
    asm("     ESTOP0");                 // Test failed!! Stop!
    for (;;);
}

interrupt void scicTxFifoIsr(void)
{
    enteredTXISR = enteredTXISR +1;
    Uint16 i;
    for(i= 0; i < 2; i++)
    {
       ScicRegs.SCITXBUF = sdataA[i];     // Send data
    }

    for(i= 0; i < 2; i++)                 //Increment send data for next cycle
    {
       sdataA[i] = (sdataA[i]+1) & 0x00FF;
    }

    ScicRegs.SCIFFTX.bit.TXFFINTCLR = 1;  // Clear SCI Interrupt flag
    PieCtrlRegs.PIEACK.all |= 0x80;      // Issue PIE ACK
}

interrupt void scicRxFifoIsr(void)
{
    enteredRXISR = enteredRXISR + 1;
    Uint16 i;
    for(i = 0; i < 2; i++)
    {
       rdataA[i] = ScicRegs.SCIRXBUF.all;        // Read data
    }
    for(i = 0; i < 2; i++)                     // Check received data
    {
       if(rdataA[i] != ((rdata_pointA+i) & 0x00FF)) error();
    }
    rdata_pointA = (rdata_pointA+1) & 0x00FF;

    ScicRegs.SCIFFRX.bit.RXFFOVRCLR = 1;   // Clear Overflow flag
    ScicRegs.SCIFFRX.bit.RXFFINTCLR = 1;   // Clear Interrupt flag

    PieCtrlRegs.PIEACK.all |= 0x80;       // Issue PIE ack
}

void scic_fifo_init()
{
    ScicRegs.SCICCR.all = 0x0007;   // 1 stop bit,  No loopback
                                   // No parity,8 char bits,
                                   // async mode, idle-line protocol
    ScicRegs.SCICTL1.all = 0x0003;  // enable TX, RX, internal SCICLK,
                                   // Disable RX ERR, SLEEP, TXWAKE
    ScicRegs.SCICTL2.bit.TXINTENA = 1;
    ScicRegs.SCICTL2.bit.RXBKINTENA = 1;
    SciaRegs.SCIHBAUD = SCI_PRD;
    ScicRegs.SCILBAUD = SCI_PRD;
    ScicRegs.SCICCR.bit.LOOPBKENA = 1; // Enable loop back
    ScicRegs.SCIFFTX.all = 0xC022;
    ScicRegs.SCIFFRX.all = 0x0022;
    ScicRegs.SCIFFCT.all = 0x00;

    ScicRegs.SCICTL1.all = 0x0023;     // Relinquish SCI from Reset
    ScicRegs.SCIFFTX.bit.TXFIFOXRESET = 1;
    ScicRegs.SCIFFRX.bit.RXFIFORESET = 1;
}

//
// End of file.
//