[参考译文] TMS320F28379D：针对 CPU1和 CPU2对闪存重新编程

EALLOW;
DevCfgRegs.CPUSEL6.bit.SPI_A = 1;           // SPIA controlled by CPU2
EDIS;

IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);

//
// Illegal Operation Trap
//
interrupt void ILLEGAL_ISR(void)
{
    //
    // Insert ISR Code here
    //

    //
    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    //
    asm ("      ESTOP0");
    for(;;);
}

        EALLOW;
        WdRegs.SCSR.all = 0x0000; // Configuration : Generate a reset signal
        EDIS;

        EALLOW;
        WdRegs.WDKEY.all = 0x0055; // Clear the WDCNTR bits
        WdRegs.WDKEY.all = 0x00AA; // Clear the WDCNTR bits
        EDIS;

        EALLOW;
        WdRegs.WDCR.all = 0x0028; // Enable the watchdog
        EDIS;

        EALLOW;
        WdRegs.WDKEY.all = 0x0055; // Do not clear the WDCNTR bits to generate the reset signal
        WdRegs.WDKEY.all = 0x0000; // Do not clear the WDCNTR bits to generate the reset signal
        EDIS;

CpuSysRegs.RESC.bit.WDRSn = 1;

//IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);

IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);

MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

    BEGIN           	: origin = 0x080000, length = 0x000002
    RAMM0           	: origin = 0x000122, length = 0x0002DE
    RAMD0           	: origin = 0x00B000, length = 0x000800
    RAMLS03          : origin = 0x008000, length = 0x002000
    //RAMLS0          	: origin = 0x008000, length = 0x000800
    //RAMLS1          	: origin = 0x008800, length = 0x000800
    //RAMLS2      		: origin = 0x009000, length = 0x000800
    //RAMLS3      		: origin = 0x009800, length = 0x000800
    RESET           	: origin = 0x3FFFC0, length = 0x000002
   
    /* Flash sectors */
    FLASHABCDEFG       : origin = 0x080002, length = 0x01FFFE		/* on-chip Flash */
    //FLASHA           : origin = 0x080002, length = 0x001FFE		/* on-chip Flash */
    //FLASHB           : origin = 0x082000, length = 0x002000		/* on-chip Flash */
    //FLASHC           : origin = 0x084000, length = 0x002000		/* on-chip Flash */
    //FLASHD           : origin = 0x086000, length = 0x002000		/* on-chip Flash */
    //FLASHE           : origin = 0x088000, length = 0x008000		/* on-chip Flash */
    //FLASHF           : origin = 0x090000, length = 0x008000		/* on-chip Flash */
    //FLASHG           : origin = 0x098000, length = 0x008000		/* on-chip Flash */
    FLASHH           : origin = 0x0A0000, length = 0x008000			/* on-chip Flash */
    //FLASHI           : origin = 0x0A8000, length = 0x008000			/* on-chip Flash */

    FLASHK           : origin = 0x0B8000, length = 0x002000			/* on-chip Flash */
    FLASHL           : origin = 0x0BA000, length = 0x002000			/* on-chip Flash */
    FLASHM           : origin = 0x0BC000, length = 0x002000			/* on-chip Flash */
	FLASHN           : origin = 0x0BE000, length = 0x002000			/* on-chip Flash */

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

    BOOT_RSVD        : origin = 0x000002, length = 0x000120     		/* Part of M0, BOOT rom will use this for stack */
    RAMM1            : origin = 0x000400, length = 0x000400     		/* on-chip RAM block M1 */
    RAMD1            : origin = 0x00B800, length = 0x000800

    RAMLS4      		: origin = 0x00A000, length = 0x000800
    RAMLS5      		: origin = 0x00A800, length = 0x000800

    RAMGS0      		: origin = 0x00C000, length = 0x001000
    RAMGS1_2_3  		: origin = 0x00D000, length = 0x003000
    RAMGS4_5_6		: origin = 0x010000, length = 0x003000
    //RAMGS5      		: origin = 0x011000, length = 0x001000
    //RAMGS6      		: origin = 0x012000, length = 0x001000
    RAMGS7      		: origin = 0x013000, length = 0x001000
    RAMGS8      		: origin = 0x014000, length = 0x001000
    RAMGS9      		: origin = 0x015000, length = 0x001000
    RAMGS10     		: origin = 0x016000, length = 0x001000
    RAMGS11     		: origin = 0x017000, length = 0x001000
    RAMGS12     		: origin = 0x018000, length = 0x001000
    RAMGS13     		: origin = 0x019000, length = 0x001000
    RAMGS14     		: origin = 0x01A000, length = 0x001000
    RAMGS15     		: origin = 0x01B000, length = 0x001000

    CPU2TOCPU1RAM   	: origin = 0x03F800, length = 0x000400
    CPU1TOCPU2RAM   	: origin = 0x03FC00, length = 0x000400

	FLASHI           : origin = 0x0A8000, length = 0x008000			/* on-chip Flash */       // for reboot mode
    FLASHJ           : origin = 0x0B0000, length = 0x008000			/* on-chip Flash */

}


SECTIONS
{
   /* Allocate program areas: */
   //.cinit			: > FLASHABCDEFG		PAGE = 0, ALIGN(4)		/* initialization values for global and static variables */
   //.pinit          	: > FLASHABCDEFG,		PAGE = 0, ALIGN(4)		/* tables for global constructors (C++) */
   //.text        	: > FLASHABCDEFG		PAGE = 0, ALIGN(4)		/* Executable code and constants */
   //codestart       	: > BEGIN				PAGE = 0, ALIGN(4)
   .cinit			: > FLASHABCDEFG		PAGE = 0, ALIGN(8)		/* initialization values for global and static variables */
   .pinit          	: > FLASHABCDEFG,		PAGE = 0, ALIGN(8)		/* tables for global constructors (C++) */
   .text        	: > FLASHABCDEFG		PAGE = 0, ALIGN(8)		/* Executable code and constants */
   codestart       	: > BEGIN				PAGE = 0, ALIGN(8)

   /* Allocate uninitalized data sections: */
   //.stack          	: > RAMM1        		PAGE = 1				/* stack space */
   //.ebss         	: >> RAMLS4 |  RAMLS5	PAGE = 1				/* global and static variables */
   //.esysmem        	: > RAMGS0       		PAGE = 1				/* memory for far malloc functions */
   .stack          	: > RAMM1        		PAGE = 1, ALIGN(8)				/* stack space */
   .ebss         	: >> RAMLS4 |  RAMLS5	PAGE = 1, ALIGN(8)				/* global and static variables */
   .esysmem        	: > RAMGS0       		PAGE = 1, ALIGN(8)				/* memory for far malloc functions */

   /* Initalized sections go in Flash */
   //.econst        	: >> FLASHABCDEFG		PAGE = 0, ALIGN(4)
   //.switch        	: > FLASHABCDEFG      	PAGE = 0, ALIGN(4)
   .econst        	: >> FLASHABCDEFG		PAGE = 0, ALIGN(8)
   .switch        	: > FLASHABCDEFG      	PAGE = 0, ALIGN(8)

   .reset         	: > RESET,     PAGE = 0, TYPE = DSECT 			/* not used, */

#ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
        GROUP
        {
            .TI.ramfunc
            { -l F021_API_F2837xD.lib}

        } LOAD = FLASHABCDEFG,
          RUN  = RAMLS03,
          LOAD_START(_RamfuncsLoadStart),
          LOAD_SIZE(_RamfuncsLoadSize),
          LOAD_END(_RamfuncsLoadEnd),
          RUN_START(_RamfuncsRunStart),
          RUN_SIZE(_RamfuncsRunSize),
          RUN_END(_RamfuncsRunEnd),
          PAGE = 0
    #else
        GROUP
        {
            ramfuncs
            { -l F021_API_F2837xD.lib}

        } LOAD = FLASHABCDEFG,
          RUN  = RAMLS03,
          LOAD_START(_RamfuncsLoadStart),
          LOAD_SIZE(_RamfuncsLoadSize),
          LOAD_END(_RamfuncsLoadEnd),
          RUN_START(_RamfuncsRunStart),
          RUN_SIZE(_RamfuncsRunSize),
          RUN_END(_RamfuncsRunEnd),
          PAGE = 0
    #endif
#endif


    /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }
   
	//CPU1ExchangeBuffer : > RAMD1			PAGE = 1
   	//CPU1toCPU2Buffer : > CPU1TOCPU2RAM		PAGE = 1
   	//CPU2toCPU1Buffer : > CPU2TOCPU1RAM		PAGE = 1
   	//CalibrationTable : > RAMGS4_5_6			PAGE = 1
	//SDCard_Memory : > RAMGS7       			PAGE = 1
	CPU1ExchangeBuffer : > RAMD1			PAGE = 1, ALIGN(8)
   	CPU1toCPU2Buffer : > CPU1TOCPU2RAM		PAGE = 1, ALIGN(8)
   	CPU2toCPU1Buffer : > CPU2TOCPU1RAM		PAGE = 1, ALIGN(8)
   	CalibrationTable : > RAMGS4_5_6			PAGE = 1, ALIGN(8)
	SDCard_Memory : > RAMGS7       			PAGE = 1, ALIGN(8)
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/