[参考译文] LAUNCHXL-F28379D：F28379D 和 Arduino 之间的 SPI 通信

void main(void)
{

//
// Step 1. Initialize System Control:
//
   InitSysCtrl();

//
// Step 2. Initialize GPIO:
//
   SpicInitGpio();

//
// Step 3. Initialize PIE vector table:
// Disable and clear all CPU interrupts
//
   DINT;
   IER = 0x0000;
   IFR = 0x0000;

//
// Initialize PIE control registers to their default state:
//
   InitPieCtrl();

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
   InitPieVectTable();

//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
   EALLOW;  // This is needed to write to EALLOW protected registers
   PieVectTable.SPIC_RX_INT = &spicRxFIFOISR;
   EDIS;    // This is needed to disable write to EALLOW protected registers

//
// Step 4. Initialize the Device Peripherals:
//
   spi_fifo_init();   // Initialize the SPI only

//
// Step 5. User specific code, enable interrupts:
//

//
// Enable interrupts required for this example
//
   PieCtrlRegs.PIECTRL.bit.ENPIE = 1;     // Enable the PIE block
   PieCtrlRegs.PIEIER6.bit.INTx9 = 1;     // Enable PIE Group 6, INT 9
   IER=0x20;                              // Enable CPU INT6
   EINT;                                  // Enable Global Interrupts

//
// Step 6. IDLE loop. Just sit and loop forever (optional):
//
    for(;;);
}


//
// spi_fifo_init - Initialize SPI FIFO
//
void spi_fifo_init()
{
    //
    // Initialize SPI FIFO registers
    //
    SpicRegs.SPIFFTX.all = 0xE082;    // Enable FIFOs, set TX FIFO level to 2
    SpicRegs.SPIFFRX.all = 0x24A2;    // Set RX FIFO level to 2
    SpicRegs.SPIFFCT.all = 0x0000;


    //
    // Initialize core SPI registers
    //
    SpiInit();
}


//
// spiRxFifoIsr - ISR for SPI receive FIFO
//
interrupt void spicRxFIFOISR(void)
{
    counter++;
    rdata=(SpicRegs.SPIDAT);     // Read data
    rdata=rdata%256;
    rdata=(rdata<<4);

    SpicRegs.SPIFFRX.bit.RXFFOVFCLR=1;  // Clear Overflow flag
    SpicRegs.SPIFFRX.bit.RXFFINTCLR=1;  // Clear Interrupt flag
       PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
}


void SpicInitGpio()
{
   EALLOW;

    //
    // Enable internal pull-up for the selected pins
    //
    // Pull-ups can be enabled or disabled by the user.
    // This will enable the pullups for the specified pins.
    // Comment out other unwanted lines.
    //
   GpioCtrlRegs.GPDPUD.bit.GPIO122 = 0; // Enable pull-up on GPIO122 (SPISIMOC)
   GpioCtrlRegs.GPDPUD.bit.GPIO123 = 0; // Enable pull-up on GPIO123 (SPISOMIC)
   GpioCtrlRegs.GPDPUD.bit.GPIO124 = 0; // Enable pull-up on GPIO124 (SPICLKC)
   GpioCtrlRegs.GPDPUD.bit.GPIO125 = 0; // Enable pull-up on GPIO125 (SPISTEC)

   GpioCtrlRegs.GPDQSEL2.bit.GPIO122 = 3; // Asynch input GPIO122 (SPISIMOC)
   GpioCtrlRegs.GPDQSEL2.bit.GPIO123 = 3; // Asynch input GPIO123 (SPISOMIC)
   GpioCtrlRegs.GPDQSEL2.bit.GPIO124 = 3; // Asynch input GPIO124 (SPICLKC)
   GpioCtrlRegs.GPDQSEL2.bit.GPIO125 = 3; // Asynch input GPIO125 (SPISTEC)

   GpioCtrlRegs.GPDMUX2.bit.GPIO122 = 2; // Configure GPIO122 as SPISIMOC
   GpioCtrlRegs.GPDMUX2.bit.GPIO123 = 2; // Configure GPIO123 as SPISOMIC
   GpioCtrlRegs.GPDMUX2.bit.GPIO124 = 2; // Configure GPIO124 as SPICLKC
   GpioCtrlRegs.GPDMUX2.bit.GPIO125 = 2; // Configure GPIO125 as SPISTEC

   GpioCtrlRegs.GPDGMUX2.bit.GPIO122 = 1; // Configure GPIO122 as SPISIMOC
   GpioCtrlRegs.GPDGMUX2.bit.GPIO123 = 1; // Configure GPIO123 as SPISOMIC
   GpioCtrlRegs.GPDGMUX2.bit.GPIO124 = 1; // Configure GPIO124 as SPICLKC
   GpioCtrlRegs.GPDGMUX2.bit.GPIO125 = 1; // Configure GPIO125 as SPISTEC




    EDIS;

}

void SpiInit(void)
{

    // Set the baud rate
        SpicRegs.SPIBRR.bit.SPI_BIT_RATE = 0x0001;
    // Halting on a breakpoint will not halt the SPI
        SpicRegs.SPIPRI.bit.FREE = 1;




        //When changing configuration, you should clear this bit before the changes and set this bit before resuming operation.
        SpicRegs.SPICCR.bit.SPISWRESET = 1;
        //(Shift Clock Polarity) This bit controls the polarity of the SPICLK signal. CLOCK POLARITY and POLARITY CLOCK PHASE (SPICTL.3) control four clocking schemes on the SPICLK pin.
        SpicRegs.SPICCR.bit.CLKPOLARITY = 0;
        //(Character Length Control Bits)the number of bits to be shifted in or SPI CHAR0 out as a single character during one shift sequence.
        SpicRegs.SPICCR.bit.SPICHAR = 7;//( 8-bit f bits to be shifted in or SPI CHAR0)

        //SPI is configured as a slave
        SpicRegs.SPICTL.bit.MASTER_SLAVE = 0;
        //Enables transmission
        SpicRegs.SPICTL.bit.TALK =0;
        //SPI Clock Phase Select
        SpicRegs.SPICTL.bit.CLK_PHASE = 0;

}

//
// End of file
//