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器件型号：TMS320F280049C 您好、香榭丽舍
我向我们的客户询问这一点。
由于 LS RAM 可以加密、CLA 到 CPU 不能加密。 这种理解是否正确？
加密区域可以访问 CPU 到 CLA RAM、也就是说、加密 CLA 区域可以获取从 CPU 传输的数据
但 CPU 无法通过 CLA 到 CPU RAM 在 CLA 中获取加密数据
2. 客户现在遇到的问题是、当他们不使用 DCSM 时、代码运行正常、但在使用 DCSM 之后、当代码未经解密而运行时、加密的 CLA 无法访问 CPU 到 CLA 的数据(DAC 输出的数据、输出为0)。
我检查了客户的.cmd 文件的配置、不应出现未加密 RAM 访问加密 RAM 的错误。 您会帮助分析原因吗？ 谢谢！
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to Flash" bootloader mode */
/* not boot used*/
BEGIN : origin = 0x080000, length = 0x000002
CLA_PROG_RAM : origin = 0x008000, length = 0x003800
RESET : origin = 0x3FFFC0, length = 0x000002
RAMGS1 : origin = 0x00E000, length = 0x002000
RAMGS2 : origin = 0x010000, length = 0x002000
/* Flash sectors */
/* BANK 0 */
HEADERINFO : origin = 0x084000, length = 0x000100, fill 0xFFFF /* on-chip Flash */
CPU_PROG_FLASH : origin = 0x084102, length = 0x00BEFE/* on-chip Flash */
/* BANK 1 */
CLA_PROG_FLASH : origin = 0x090000, length = 0x004000 /* on-chip Flash */
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000 /* on-chip Flash */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMLS7 : origin = 0x00B800, length = 0x0007F8
RAM_STACK : origin = 0x00C000, length = 0x000C00
RAMGS0 : origin = 0x00CC00, length = 0x001400
RAMGS3 : origin = 0x012000, length = 0x002000
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0, ALIGN(4)
.text : >>CPU_PROG_FLASH, PAGE = 0, ALIGN(4)
.cinit : > CPU_PROG_FLASH, PAGE = 0, ALIGN(4)
.pinit : > CPU_PROG_FLASH, PAGE = 0, ALIGN(4)
.switch : > CPU_PROG_FLASH, PAGE = 0, ALIGN(4)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
.cio : > RAMGS1, PAGE = 0
.stack : > RAM_STACK, PAGE = 1
.ebss : > RAMGS0, PAGE = 1
.esysmem : > RAMGS3, PAGE = 1
.econst : > CPU_PROG_FLASH, PAGE = 0, ALIGN(4)
ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS3, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
/* CLA specific sections */
Cla1Prog : LOAD = CLA_PROG_FLASH,
RUN = CLA_PROG_RAM,
LOAD_START(_Cla1ProgLoadStart),
RUN_START(_Cla1ProgRunStart),
LOAD_SIZE(_Cla1ProgLoadSize),
PAGE = 0, ALIGN(4)
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
/*.TI.ramfunc : LOAD = CPU_PROG_FLASH, */
GROUP
{
.TI.ramfunc
{ -l F021_API_F28004x_FPU32.lib}
} LOAD = CPU_PROG_FLASH,
RUN = RAMGS1 | RAMGS2,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
.scratchpad : > RAMLS7, PAGE = 1
.bss_cla : > RAMLS7, PAGE = 1
Cla1DataRam : > RAMLS7, PAGE = 1
.const_cla : LOAD = CLA_PROG_FLASH,
RUN = CLA_PROG_RAM,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize),
PAGE = 0
CodeInfoFile : > HEADERINFO, PAGE = 0
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
此致、
Julia
