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器件型号：TMS320F28379D 大家好、我的 ePWM 有问题、我同时启动它们、但 PWM1与 PWM2和 PWM3有异步、我没有发现 我的错误您知道我的错误在哪里吗？
图 Ehe PWM 应该是50/50的、黄色是 PWM1和绿色 PWM2。 PWM3与 PWM2相同；
GpioCtrlRegs.GPACSEL1.all = 0x00222222; GpioCtrlRegs.GPACSEL2.all = 0x00000000; CpuSysRegs.PCLKCR0.bit.GTBCLKSYNC = 0; // Stop all the TB clocks EDIS; ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0; // // EPWM Module 4 config PWM1.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Up count mode PWM1.TBPHS.bit.TBPHS = 0; // Set Phase register to zero PWM1.TBCTL.bit.PHSEN = TB_DISABLE; // Master module PWM1.TBCTL.bit.PRDLD = TB_SHADOW; PWM1.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module PWM1.TBCTL.bit.HSPCLKDIV = TB_DIV1; //(int) PWM_CLK_PRESCALER/4;// High Speed Time-base Clock Prescale Bits 1 PWM1.TBCTL.bit.FREE_SOFT = 2; // Emulation Mode Bits = Free run PWM1.AQCTLA.all = AQ_NO_ACTION; // clear AQ events PWM1.AQCTLB.all = AQ_NO_ACTION; // clear AQ events PWM1.AQCTLA.bit.CAU = AQ_SET; // force EPWM1A HIGH when counter equals CMPA and counts up PWM1.AQCTLA.bit.CBU = AQ_CLEAR; // force EPWM1A HIGH when counter equals CMPB and counts up PWM1.AQCTLB.bit.CAU = AQ_SET; // force EPWM1B LOW when counter equals CMPA and counts up PWM1.AQCTLB.bit.CBU = AQ_CLEAR; // force EPWM1B HIGH when counter equals CMPB and counts up PWM1.DBFED.all = PWM_TOTZEIT_CNT; // Falling Edge Delay PWM1.DBRED.all = PWM_TOTZEIT_CNT; // Rising Edge Delay PWM1.DBCTL.bit.IN_MODE = 2; PWM1.DBCTL.bit.POLSEL = 2; // Active high complementary (AHC) mode. EPWMxB is inverted PWM1.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB PWM1.CMPCTL.bit.SHDWAMODE = CC_SHADOW; PWM1.CMPCTL.bit.SHDWBMODE = CC_SHADOW; PWM1.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero PWM1.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero PWM1.TBPRD = (int) (periode_us * PWM_FREQUENZ_IN_MHz); PWM1.ETSEL.all = 0x0009; // Interrupt für Kurz-Task PWM1.ETPS.all = 0x0001; // Interrupt für Kurz-Task // //======================== // // EPWM Module 5 config PWM2.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Up count mode PWM2.TBPHS.bit.TBPHS = 0; // Set Phase register to zero PWM2.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module PWM2.TBCTL.bit.PRDLD = TB_SHADOW; PWM2.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; PWM2.TBCTL.bit.HSPCLKDIV = TB_DIV1;// (int) PWM_CLK_PRESCALER/4;// High Speed Time-base Clock Prescale Bits 1 PWM2.TBCTL.bit.FREE_SOFT = 2; // Emulation Mode Bits = Free run PWM2.AQCTLA.all = AQ_NO_ACTION; // clear AQ events PWM2.AQCTLB.all = AQ_NO_ACTION; // clear AQ events PWM2.AQCTLA.bit.CAU = AQ_SET; // force EPWM2A HIGH when counter equals CMPA and counts up PWM2.AQCTLA.bit.CBU = AQ_CLEAR; // force EPWM2A HIGH when counter equals CMPB and counts up PWM2.AQCTLB.bit.CAU = AQ_SET; // force EPWM2B LOW when counter equals CMPA and counts up PWM2.AQCTLB.bit.CBU = AQ_CLEAR; // force EPWM2B HIGH when counter equals CMPB and counts up PWM2.DBFED.all = PWM_TOTZEIT_CNT; // Falling Edge Delay PWM2.DBRED.all = PWM_TOTZEIT_CNT; // Rising Edge Delay PWM2.DBCTL.bit.IN_MODE = 2; PWM2.DBCTL.bit.POLSEL = 2; // Active high complementary (AHC) mode. EPWMxB is inverted PWM2.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB PWM2.CMPCTL.bit.SHDWAMODE = CC_SHADOW; PWM2.CMPCTL.bit.SHDWBMODE = CC_SHADOW; PWM2.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero PWM2.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero PWM2.TBPRD = (int) (periode_us * PWM_FREQUENZ_IN_MHz); // //======================== // // EPWM Module 6 config PWM3.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Up count mode PWM3.TBPHS.bit.TBPHS = 0; // Set Phase register to zero PWM3.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module PWM3.TBCTL.bit.PRDLD = TB_SHADOW; PWM3.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; PWM3.TBCTL.bit.HSPCLKDIV = TB_DIV1;// (int) PWM_CLK_PRESCALER/4;// High Speed Time-base Clock Prescale Bits 1 PWM3.TBCTL.bit.FREE_SOFT = 2; // Emulation Mode Bits = Free run PWM3.AQCTLA.all = AQ_NO_ACTION; // clear AQ events PWM3.AQCTLB.all = AQ_NO_ACTION; // clear AQ events PWM3.AQCTLA.bit.CAU = AQ_SET; // force EPWM3A HIGH when counter equals CMPA and counts up PWM3.AQCTLA.bit.CBU = AQ_CLEAR; // force EPWM3A HIGH when counter equals CMPB and counts up PWM3.AQCTLB.bit.CAU = AQ_SET; // force EPWM3B LOW when counter equals CMPA and counts up PWM3.AQCTLB.bit.CBU = AQ_CLEAR; // force EPWM3B HIGH when counter equals CMPB and counts up PWM3.DBFED.all = PWM_TOTZEIT_CNT; // Falling Edge Delay PWM3.DBRED.all = PWM_TOTZEIT_CNT; // Rising Edge Delay PWM3.DBCTL.bit.IN_MODE = 2; PWM3.DBCTL.bit.POLSEL = 2; // Active high complementary (AHC) mode. EPWMxB is inverted PWM3.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB PWM3.CMPCTL.bit.SHDWAMODE = CC_SHADOW; PWM3.CMPCTL.bit.SHDWBMODE = CC_SHADOW; PWM3.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero PWM3.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero PWM3.TBPRD = (int) (periode_us * PWM_FREQUENZ_IN_MHz); // ##### set to CPU2 ################ EALLOW; DevCfgRegs.CPUSEL0.bit.EPWM1 = 1; DevCfgRegs.CPUSEL0.bit.EPWM2 = 1; DevCfgRegs.CPUSEL0.bit.EPWM3 = 1; EDIS;
