[参考译文] TMS320F280039：CLB 似乎不工作

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Other Parts Discussed in Thread: SYSCONFIG

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1343914/tms320f280039-clb-seems-not-work

器件型号：TMS320F280039
主题中讨论的其他器件：SysConfig

尊敬的先生：

将代码迁移到我的项目后、我发现它没有输出到 GPIO、然后我尝试 CLB 的 out0上的"always 1"、发现 GPIO 仍然为0。下面是代码：

启用 CLB1 CLK

CpuSysRegs.PCLKCR17.bit.CLB1 = 1;
CpuSysRegs.PCLKCR17.bit.CLB2 = 0;
CpuSysRegs.PCLKCR17.bit.CLB3 = 0;
CpuSysRegs.PCLKCR17.bit.CLB4 = 0;

CLB 初始化

EALLOW;

//Board_init begin.........................................................
//CLB_init.................................................................
//CLB output en
Clb1LogicCtrlRegs.CLB_OUT_EN = 0;
Clb1LogicCfgRegs.CLB_MISC_ACCESS_CTRL.bit.BLKEN = 0; //CLB_enableOutputMaskUpdates

// myCLB0 CLB_IN0/1 initialization
//
// The following functions configure the CLB input mux and whether the inputs
// have synchronization or pipeline enabled; check the device manual for more
// information on when a signal needs to be synchronized or go through a
// pipeline filter
//
Clb1LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.LCL_MUX_SEL_IN_0 = 0; //CLB1_GLB_MUX_OUT
Clb1LogicCtrlRegs.CLB_LCL_MUX_SEL_1.bit.LCL_MUX_SEL_IN_1 = 0; //CLB1_GLB_MUX_OUT
Clb1LogicCtrlRegs.CLB_GLBL_MUX_SEL_1.bit.GLBL_MUX_SEL_IN_0 = 64; //CLB_GLOBAL_IN_MUX_CLB_AUXSIG0
Clb1LogicCtrlRegs.CLB_GLBL_MUX_SEL_1.bit.GLBL_MUX_SEL_IN_1 = 65; //CLB_GLOBAL_IN_MUX_CLB_AUXSIG1
Clb1LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_0 = 0; //Input comes from selected external input
Clb1LogicCtrlRegs.CLB_IN_MUX_SEL_0.bit.SEL_GP_IN_1 = 0; //Input comes from selected external input
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.SYNC0 = 1; //enable sync for in0
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.SYNC1 = 1; //enable sync for in1
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.FIN0 = 0; //no filter
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.FIN1 = 0; //no filter
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.PIPE0 = 0; //CLB_disableInputPipelineMode
Clb1LogicCtrlRegs.CLB_INPUT_FILTER.bit.PIPE1 = 0; //CLB_disableInputPipelineMode

//CLB_setGPREG
Clb1LogicCtrlRegs.CLB_GP_REG.all = 0;
//CLB_enableCLB
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.GLOBAL_EN = 1;

//CLB_OUTPUTXBAR_init......................................................
ClbOutputXbarRegs.OUTPUTLATCHENABLE.bit.OUTPUT8 = 0; //disable latch
ClbOutputXbarRegs.OUTPUTINV.bit.OUTPUT8 = 0; //don't invert
ClbOutputXbarRegs.OUTPUT8MUX0TO15CFG.bit.MUX0 = 0; // CLB1 out0
ClbOutputXbarRegs.OUTPUT8MUXENABLE.bit.MUX0 = 1;
ClbOutputXbarRegs.OUTPUTLATCHENABLE.bit.OUTPUT7 = 0; //disable latch
ClbOutputXbarRegs.OUTPUTINV.bit.OUTPUT7 = 0; //don't invert
ClbOutputXbarRegs.OUTPUT7MUX0TO15CFG.bit.MUX2 = 0; // CLB1 out2
ClbOutputXbarRegs.OUTPUT7MUXENABLE.bit.MUX2 = 1;

//CLBXBAR_init.............................................................
// AUXSIG0 and AUXSIG1 configure
ClbXbarRegs.AUXSIG0MUX0TO15CFG.bit.MUX6 = 0; //CMPSS4_CTRIPH
ClbXbarRegs.AUXSIG1MUX0TO15CFG.bit.MUX7 = 0; //CMPSS4_CTRIPL
ClbXbarRegs.AUXSIG0MUXENABLE.bit.MUX6 = 1;
ClbXbarRegs.AUXSIG1MUXENABLE.bit.MUX7 = 1;
//Board_init end...........................................................

//
// Disable Pipeline Mode
//
// CLB_disablePipelineMode(base);
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.PIPELINE_EN = 0;
//
// Output LUT
//
//
// Equation for Output Look-Up Table Block 0 for TILE1: i0
//
//CLB_configOutputLUT(base, CLB_OUT0, TILE1_CFG_OUTLUT_0);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_0.bit.IN0 = 8; //Always 1 on out0

//
// Equation for Output Look-Up Table Block 1 for TILE1: i0
//
//CLB_configOutputLUT(base, CLB_OUT1, TILE1_CFG_OUTLUT_1);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_1.bit.IN0 = 4; //FSM_0 STATE_BIT_0

//
// Equation for Output Look-Up Table Block 2 for TILE1: i0
//
//CLB_configOutputLUT(base, CLB_OUT2, TILE1_CFG_OUTLUT_2);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_2.bit.IN0 = 25; 

//
// Equation for Output Look-Up Table Block 3 for TILE1: i0
//
//CLB_configOutputLUT(base, CLB_OUT3, TILE1_CFG_OUTLUT_3);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_3.bit.IN0 = 12; //FSM_1 STATE_BIT_0


//CLB_configOutputLUT(base, CLB_OUT4, TILE1_CFG_OUTLUT_4);
Clb1LogicCfgRegs.CLB_OUTPUT_LUT_4.bit.IN0 = 8;
//CLB_configOutputLUT(base, CLB_OUT5, TILE1_CFG_OUTLUT_5);

//CLB_configOutputLUT(base, CLB_OUT6, TILE1_CFG_OUTLUT_6);

//CLB_configOutputLUT(base, CLB_OUT7, TILE1_CFG_OUTLUT_7);

//
// AOC
//
//CLB_configAOC(base, CLB_AOC0, TILE1_OUTPUT_COND_CTR_0);
//CLB_configAOC(base, CLB_AOC1, TILE1_OUTPUT_COND_CTR_1);
//CLB_configAOC(base, CLB_AOC2, TILE1_OUTPUT_COND_CTR_2);
//CLB_configAOC(base, CLB_AOC3, TILE1_OUTPUT_COND_CTR_3);
//CLB_configAOC(base, CLB_AOC4, TILE1_OUTPUT_COND_CTR_4);
//CLB_configAOC(base, CLB_AOC5, TILE1_OUTPUT_COND_CTR_5);
//CLB_configAOC(base, CLB_AOC6, TILE1_OUTPUT_COND_CTR_6);
//CLB_configAOC(base, CLB_AOC7, TILE1_OUTPUT_COND_CTR_7);

//
// LUT 0 - 2 are configured as macros in clb_config.h; these macros are used in
// CLB_selectLUT4Inputs and CLB_configLUT4Function
//

//
// LUT Configuration
//
//CLB_selectLUT4Inputs(base, TILE1_CFG_LUT4_IN0, TILE1_CFG_LUT4_IN1, TILE1_CFG_LUT4_IN2, TILE1_CFG_LUT4_IN3);
//CLB_configLUT4Function(base, TILE1_CFG_LUT4_FN10, TILE1_CFG_LUT4_FN2);

//
// FSM 0 - 2 are configured in <file>
//
// State 0 output equation for Finite State Machine 0 for TILE1: ((~s0)&e0)|(s0&e1)
// User Description for Finite State Machine 0 for TILE1
/*
complementary ePWMA
*/
// State 0 output equation for Finite State Machine 1 for TILE1: ((~s0)&e0)|(s0&(~e1))
// User Description for Finite State Machine 1 for TILE1
/*
complementary ePWMB
*/

//
// FSM
//
//CLB_selectFSMInputs(base, TILE1_CFG_FSM_EXT_IN0, TILE1_CFG_FSM_EXT_IN1, TILE1_CFG_FSM_EXTRA_IN0, TILE1_CFG_FSM_EXTRA_IN1);
//CLB_configFSMNextState(base, TILE1_CFG_FSM_NEXT_STATE_0, TILE1_CFG_FSM_NEXT_STATE_1, TILE1_CFG_FSM_NEXT_STATE_2);
//CLB_configFSMLUTFunction(base, TILE1_CFG_FSM_LUT_FN10, TILE1_CFG_FSM_LUT_FN2);

Clb1LogicCfgRegs.CLB_FSM_EXTERNAL_IN0.all = TILE1_CFG_FSM_EXT_IN0;
Clb1LogicCfgRegs.CLB_FSM_EXTERNAL_IN1.all = TILE1_CFG_FSM_EXT_IN1;
Clb1LogicCfgRegs.CLB_FSM_EXTRA_IN0.all = TILE1_CFG_FSM_EXTRA_IN0;
Clb1LogicCfgRegs.CLB_FSM_EXTRA_IN1.all = TILE1_CFG_FSM_EXTRA_IN1;
Clb1LogicCfgRegs.CLB_FSM_NEXT_STATE_0.all = TILE1_CFG_FSM_NEXT_STATE_0;
Clb1LogicCfgRegs.CLB_FSM_NEXT_STATE_1.all = TILE1_CFG_FSM_NEXT_STATE_1;
Clb1LogicCfgRegs.CLB_FSM_NEXT_STATE_2.all = TILE1_CFG_FSM_NEXT_STATE_2;
Clb1LogicCfgRegs.CLB_FSM_LUT_FN1_0.all = TILE1_CFG_FSM_LUT_FN10;
Clb1LogicCfgRegs.CLB_FSM_LUT_FN2.all = TILE1_CFG_FSM_LUT_FN2;
//
// Counter 0 - 2 are configured in <file>
//
// User Description for Counter 0 for TILE1
/*
reset counter with input 0(CMPSS4 TRIPH) and load with input 1(CMPSS4 TRIP-
L)
*/
// User Description for Counter 1 for TILE1
/*
PWMA
*/
// User Description for Counter 2 for TILE1
/*
PWMB
*/

//
// Counters
//
//CLB_selectCounterInputs(base, TILE1_CFG_COUNTER_RESET, TILE1_CFG_COUNTER_EVENT, TILE1_CFG_COUNTER_MODE_0, TILE1_CFG_COUNTER_MODE_1);
//CLB_configMiscCtrlModes(base, TILE1_CFG_MISC_CONTROL);
//CLB_configCounterLoadMatch(base, CLB_CTR0, TILE1_COUNTER_0_LOAD_VAL, TILE1_COUNTER_0_MATCH1_VAL, TILE1_COUNTER_0_MATCH2_VAL);
//CLB_configCounterLoadMatch(base, CLB_CTR1, TILE1_COUNTER_1_LOAD_VAL, TILE1_COUNTER_1_MATCH1_VAL, TILE1_COUNTER_1_MATCH2_VAL);
//CLB_configCounterLoadMatch(base, CLB_CTR2, TILE1_COUNTER_2_LOAD_VAL, TILE1_COUNTER_2_MATCH1_VAL, TILE1_COUNTER_2_MATCH2_VAL);
//CLB_configCounterTapSelects(base, TILE1_CFG_TAP_SEL);

Clb1LogicCfgRegs.CLB_COUNT_RESET.all = TILE1_CFG_COUNTER_RESET;
Clb1LogicCfgRegs.CLB_COUNT_EVENT.all = TILE1_CFG_COUNTER_EVENT;
Clb1LogicCfgRegs.CLB_COUNT_MODE_0.all = TILE1_CFG_COUNTER_MODE_0;
Clb1LogicCfgRegs.CLB_COUNT_MODE_1.all = TILE1_CFG_COUNTER_MODE_1;
Clb1LogicCfgRegs.CLB_MISC_CONTROL.all = TILE1_CFG_MISC_CONTROL;

Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_0_LOAD;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_0_LOAD_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_0_MATCH1;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_0_MATCH1_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_0_MATCH2;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_0_MATCH2_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;

Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_1_LOAD;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_1_LOAD_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_1_MATCH1;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_1_MATCH1_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_1_MATCH2;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_1_MATCH2_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;

Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_2_LOAD;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_2_LOAD_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_2_MATCH1;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_2_MATCH1_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;
Clb1LogicCtrlRegs.CLB_LOAD_ADDR.all = CLB_ADDR_COUNTER_2_MATCH2;
Clb1LogicCtrlRegs.CLB_LOAD_DATA = TILE1_COUNTER_2_MATCH2_VAL;
Clb1LogicCtrlRegs.CLB_LOAD_EN.bit.LOAD_EN = 1;

//
// HLC is configured in <file>
//

//
// HLC
//
//CLB_configHLCEventSelect(base, TILE1_HLC_EVENT_SEL);
//CLB_setHLCRegisters(base, TILE1_HLC_R0_INIT, TILE1_HLC_R1_INIT, TILE1_HLC_R2_INIT, TILE1_HLC_R3_INIT);

//for(i = 0; i <= CLB_NUM_HLC_INSTR; i++)
//{
// CLB_programHLCInstruction(base, i, TILE1HLCInstr[i]);
//}

EDIS;

GPIO 多路复用器

GPIO0多路复用器到11 (CLB_OUTPUTXBAR8)

EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 2;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 3; // Configure GPIO0 as CLB output
EDIS;

请提出任何想法、谢谢。

1 年多前

0 admin 1 年多前

TI__Guru**** 2337880 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Bishlant：

(如果您不反对、我会将您的代码插入到代码块中、这样就不会让这篇文章变得混乱)

Unknown 说：
将代码迁移到我的项目后、我发现它没有输出到 GPIO、然后我尝试在 CLB 的 out0上"always 1"、发现 GPIO 仍然为0。

您是否使用 SysConfig 配置 CLB/GPIO？如果是、您能否同时提供.syscfg 或一组源文件(在迁移之前和之后)？根据您的措辞、似乎之前持有此代码的器件上 GPIO 切换工作正常、是这样吗？

Unknown 说：
EALLOW；
GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 2；
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 3；//将 GPIO0配置为 CLB 输出
EDIS；

除了上述代码外、我没有看到适用于您的 GPIO 配置的任何代码、您还没有在这里提供相关内容吗？

0 admin 1 年多前

TI__Guru**** 2337880 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好、Omer：

如果你不反对的话,我会把你的代码插入一个代码块中,这样它就不会让这篇文章变得混乱。

可能由于 IT 策略、我无法在此处上传文件。我可以给你发邮件吗?

Unknown 说：
似乎 GPIO 切换在以前持有此代码的设备上运行良好，这是正确的吗？

GPIO 以前用作 ePWM、并且工作正常。

这不是 GPIO 的配置吗？有什么问题？

EALLOW；
GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 2；
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 3；//将 GPIO0配置为 CLB 输出
EDIS；

0 admin 1 年多前

TI__Guru**** 2337880 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

/*
 *  ======== clb.c ========
 *  DO NOT EDIT - This file is generated by the SysConfig tool.
 */

#include "driverlib.h"
#include "device.h"
#include "clb_config.h"
#include "clb.h"


const uint32_t TILE1_HLC_initFIFOData[4] = {TILE1_HLC_FIFO0_INIT, TILE1_HLC_FIFO1_INIT, TILE1_HLC_FIFO2_INIT, TILE1_HLC_FIFO3_INIT};

uint16_t TILE1HLCInstr[CLB_NUM_HLC_INSTR + 1] =
{
    TILE1_HLCINSTR_0,
    TILE1_HLCINSTR_1,
    TILE1_HLCINSTR_2,
    TILE1_HLCINSTR_3,
    TILE1_HLCINSTR_4,
    TILE1_HLCINSTR_5,
    TILE1_HLCINSTR_6,
    TILE1_HLCINSTR_7,
    TILE1_HLCINSTR_8,
    TILE1_HLCINSTR_9,
    TILE1_HLCINSTR_10,
    TILE1_HLCINSTR_11,
    TILE1_HLCINSTR_12,
    TILE1_HLCINSTR_13,
    TILE1_HLCINSTR_14,
    TILE1_HLCINSTR_15,
    TILE1_HLCINSTR_16,
    TILE1_HLCINSTR_17,
    TILE1_HLCINSTR_18,
    TILE1_HLCINSTR_19,
    TILE1_HLCINSTR_20,
    TILE1_HLCINSTR_21,
    TILE1_HLCINSTR_22,
    TILE1_HLCINSTR_23,
    TILE1_HLCINSTR_24,
    TILE1_HLCINSTR_25,
    TILE1_HLCINSTR_26,
    TILE1_HLCINSTR_27,
    TILE1_HLCINSTR_28,
    TILE1_HLCINSTR_29,
    TILE1_HLCINSTR_30,
    TILE1_HLCINSTR_31
};



void initTILE1(uint32_t base)
{
    uint16_t i;
    //
    //  Pipeline Mode
    //
    CLB_disablePipelineMode(base);
    //
    //  Output LUT
    //
    //
    //  Equation for Output Look-Up Table Block 0 for TILE1: i0
    //
    CLB_configOutputLUT(base, CLB_OUT0, TILE1_CFG_OUTLUT_0);

    //
    //  Equation for Output Look-Up Table Block 1 for TILE1: i0
    //
    CLB_configOutputLUT(base, CLB_OUT1, TILE1_CFG_OUTLUT_1);

    //
    //  Equation for Output Look-Up Table Block 2 for TILE1: i0
    //
    CLB_configOutputLUT(base, CLB_OUT2, TILE1_CFG_OUTLUT_2);

    //
    //  Equation for Output Look-Up Table Block 3 for TILE1: i0
    //
    CLB_configOutputLUT(base, CLB_OUT3, TILE1_CFG_OUTLUT_3);

    //
    //  Equation for Output Look-Up Table Block 4 for TILE1: i0
    //
    CLB_configOutputLUT(base, CLB_OUT4, TILE1_CFG_OUTLUT_4);

    CLB_configOutputLUT(base, CLB_OUT5, TILE1_CFG_OUTLUT_5);
    
    CLB_configOutputLUT(base, CLB_OUT6, TILE1_CFG_OUTLUT_6);

    CLB_configOutputLUT(base, CLB_OUT7, TILE1_CFG_OUTLUT_7);

    //
    //  AOC
    //
    CLB_configAOC(base, CLB_AOC0, TILE1_OUTPUT_COND_CTR_0);
    CLB_configAOC(base, CLB_AOC1, TILE1_OUTPUT_COND_CTR_1);
    CLB_configAOC(base, CLB_AOC2, TILE1_OUTPUT_COND_CTR_2);
    CLB_configAOC(base, CLB_AOC3, TILE1_OUTPUT_COND_CTR_3);
    CLB_configAOC(base, CLB_AOC4, TILE1_OUTPUT_COND_CTR_4);
    CLB_configAOC(base, CLB_AOC5, TILE1_OUTPUT_COND_CTR_5);
    CLB_configAOC(base, CLB_AOC6, TILE1_OUTPUT_COND_CTR_6);
    CLB_configAOC(base, CLB_AOC7, TILE1_OUTPUT_COND_CTR_7);

    //
    // LUT 0 - 2 are configured as macros in clb_config.h; these macros are used in
    // CLB_selectLUT4Inputs and CLB_configLUT4Function
    //

    //
    //  LUT Configuration
    //
    CLB_selectLUT4Inputs(base, TILE1_CFG_LUT4_IN0, TILE1_CFG_LUT4_IN1, TILE1_CFG_LUT4_IN2, TILE1_CFG_LUT4_IN3);
    CLB_configLUT4Function(base, TILE1_CFG_LUT4_FN10, TILE1_CFG_LUT4_FN2);

    //
    // FSM 0 - 2 are configured in <file>
    //
    //  State 0 output equation for Finite State Machine 0 for TILE1: ((~s0)&e0)|(s0&e1)
    //  User Description for Finite State Machine 0 for TILE1
    /*
        complementary ePWMA
    */
    //  State 0 output equation for Finite State Machine 1 for TILE1: ((~s0)&e0)|(s0&(~e1))
    //  User Description for Finite State Machine 1 for TILE1
    /*
        complementary ePWMB
    */

    //
    //  FSM
    //
    CLB_selectFSMInputs(base, TILE1_CFG_FSM_EXT_IN0, TILE1_CFG_FSM_EXT_IN1, TILE1_CFG_FSM_EXTRA_IN0, TILE1_CFG_FSM_EXTRA_IN1);
    CLB_configFSMNextState(base, TILE1_CFG_FSM_NEXT_STATE_0, TILE1_CFG_FSM_NEXT_STATE_1, TILE1_CFG_FSM_NEXT_STATE_2);
    CLB_configFSMLUTFunction(base, TILE1_CFG_FSM_LUT_FN10, TILE1_CFG_FSM_LUT_FN2);

    //
    // Counter 0 - 2 are configured in <file>
    //
    //  User Description for Counter 0 for TILE1
    /*
        reset counter with input 0(CMPSS4 TRIPH) and load with input 1(CMPSS4 TRIP-
		L)
    */
    //  User Description for Counter 1 for TILE1
    /*
        PWMA
    */
    //  User Description for Counter 2 for TILE1
    /*
        PWMB
    */

    //
    //  Counters
    //
    CLB_selectCounterInputs(base, TILE1_CFG_COUNTER_RESET, TILE1_CFG_COUNTER_EVENT, TILE1_CFG_COUNTER_MODE_0, TILE1_CFG_COUNTER_MODE_1);
    CLB_configMiscCtrlModes(base, TILE1_CFG_MISC_CONTROL);
    CLB_configCounterLoadMatch(base, CLB_CTR0, TILE1_COUNTER_0_LOAD_VAL, TILE1_COUNTER_0_MATCH1_VAL, TILE1_COUNTER_0_MATCH2_VAL);
    CLB_configCounterLoadMatch(base, CLB_CTR1, TILE1_COUNTER_1_LOAD_VAL, TILE1_COUNTER_1_MATCH1_VAL, TILE1_COUNTER_1_MATCH2_VAL);
    CLB_configCounterLoadMatch(base, CLB_CTR2, TILE1_COUNTER_2_LOAD_VAL, TILE1_COUNTER_2_MATCH1_VAL, TILE1_COUNTER_2_MATCH2_VAL);
    CLB_configCounterTapSelects(base, TILE1_CFG_TAP_SEL);

    //
    // HLC is configured in <file>
    //

    //
    // HLC
    //
    CLB_configHLCEventSelect(base, TILE1_HLC_EVENT_SEL);
    CLB_setHLCRegisters(base, TILE1_HLC_R0_INIT, TILE1_HLC_R1_INIT, TILE1_HLC_R2_INIT, TILE1_HLC_R3_INIT);

    for(i = 0; i <= CLB_NUM_HLC_INSTR; i++)
    {
        CLB_programHLCInstruction(base, i, TILE1HLCInstr[i]);
    }
}

0 admin 1 年多前

TI__Guru**** 2337880 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

/*
 *  ======== clb.h ========
 *  DO NOT EDIT - This file is generated by the SysConfig tool.
 */
#ifndef ti_clb_h
#define ti_clb_h

#include <stdint.h>

#ifdef __cplusplus
extern "C" {                // support C++ sources
#endif

// HLC Instruction Register Field definitions
#define HLC_OPCODE_R0 0x0
#define HLC_OPCODE_R1 0x1
#define HLC_OPCODE_R2 0x2
#define HLC_OPCODE_R3 0x3
#define HLC_OPCODE_C0 0x4
#define HLC_OPCODE_C1 0x5
#define HLC_OPCODE_C2 0x6

#define HLC_OPCODE_MOV    0x00
#define HLC_OPCODE_MOV_T1 0x01
#define HLC_OPCODE_MOV_T2 0x02
#define HLC_OPCODE_PUSH   0x03
#define HLC_OPCODE_PULL   0x04
#define HLC_OPCODE_ADD    0x05
#define HLC_OPCODE_SUB    0x06
#define HLC_OPCODE_INTR   0x07

//---------------------------------------------------------------------------
// TILE1
//---------------------------------------------------------------------------
#define TILE1_PIPELINE_MODE 0
#define TILE1_CFG_OUTLUT_0 0x550008
#define TILE1_CFG_OUTLUT_1 0x550004
#define TILE1_CFG_OUTLUT_2 0x550019
#define TILE1_CFG_OUTLUT_3 0x55000c
#define TILE1_CFG_OUTLUT_4 0x550018
#define TILE1_CFG_OUTLUT_5 0x0
#define TILE1_CFG_OUTLUT_6 0x0
#define TILE1_CFG_OUTLUT_7 0x0

#define TILE1_CFG_LUT4_IN0   0x0
#define TILE1_CFG_LUT4_IN1   0x0
#define TILE1_CFG_LUT4_IN2   0x0
#define TILE1_CFG_LUT4_IN3   0x0
#define TILE1_CFG_LUT4_FN10  ((0x00000) | 0x0)
#define TILE1_CFG_LUT4_FN2   0x0

#define TILE1_CFG_FSM_EXT_IN0      0x26b
#define TILE1_CFG_FSM_EXT_IN1      0x42
#define TILE1_CFG_FSM_EXTRA_IN0    0x0
#define TILE1_CFG_FSM_EXTRA_IN1    0x0
#define TILE1_CFG_FSM_NEXT_STATE_0 ((0x00000) | 0xfa50)
#define TILE1_CFG_FSM_NEXT_STATE_1 ((0x00000) | 0x50fa)
#define TILE1_CFG_FSM_NEXT_STATE_2 ((0x00000) | 0x0)
#define TILE1_CFG_FSM_LUT_FN10     ((0x00000) | 0x0)
#define TILE1_CFG_FSM_LUT_FN2      0x0
#define TILE1_FSM_MISC_CONTROL     0x0

#define TILE1_CFG_COUNTER_RESET   0xc38
#define TILE1_CFG_COUNTER_EVENT   0x19
#define TILE1_CFG_COUNTER_MODE_0  0x460
#define TILE1_CFG_COUNTER_MODE_1  0x2100
#define TILE1_CFG_TAP_SEL          0x0
#define TILE1_CFG_MISC_CONTROL    (0x0 | TILE1_FSM_MISC_CONTROL)

#define TILE1_COUNTER_0_MATCH1_VAL  0
#define TILE1_COUNTER_0_MATCH2_VAL  1
#define TILE1_COUNTER_0_LOAD_VAL    1
#define TILE1_COUNTER_1_MATCH1_VAL  3
#define TILE1_COUNTER_1_MATCH2_VAL  0
#define TILE1_COUNTER_1_LOAD_VAL    0
#define TILE1_COUNTER_2_MATCH1_VAL  3
#define TILE1_COUNTER_2_MATCH2_VAL  0
#define TILE1_COUNTER_2_LOAD_VAL    0


#define TILE1_SPI_EN 0

#define TILE1_HLC_EVENT_SEL 0x0
#define TILE1_HLC_R0_INIT 0
#define TILE1_HLC_R1_INIT 0
#define TILE1_HLC_R2_INIT 0
#define TILE1_HLC_R3_INIT 0

#define TILE1_HLC_FIFO0_INIT 0
#define TILE1_HLC_FIFO1_INIT 0
#define TILE1_HLC_FIFO2_INIT 0
#define TILE1_HLC_FIFO3_INIT 0

#define TILE1_HLCINSTR_0	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_1	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_2	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_3	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_4	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_5	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_6	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_7	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_8	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_9	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_10	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_11	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_12	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_13	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_14	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_15	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_16	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_17	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_18	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_19	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_20	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_21	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_22	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_23	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_24	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_25	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_26	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_27	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_28	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_29	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_30	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)
#define TILE1_HLCINSTR_31	(1 << 11 | HLC_OPCODE_MOV << 6 | HLC_OPCODE_R0<<3 | HLC_OPCODE_R0)




#define TILE1_OUTPUT_COND_CTR_0 0x0
#define TILE1_OUTPUT_COND_CTR_1 0x0
#define TILE1_OUTPUT_COND_CTR_2 0x0
#define TILE1_OUTPUT_COND_CTR_3 0x0
#define TILE1_OUTPUT_COND_CTR_4 0x0
#define TILE1_OUTPUT_COND_CTR_5 0x0
#define TILE1_OUTPUT_COND_CTR_6 0x0
#define TILE1_OUTPUT_COND_CTR_7 0x0

void initTILE1(uint32_t base);

#ifdef __cplusplus
}
#endif

#endif // ti_clb_h

它们是 clb_config.h 和.c

0 admin 1 年多前

TI__Guru**** 2337880 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Bishlant：

Unknown 说：
可能由于 IT 策略，我无法在此处上传文件。我可以邮寄给您吗？

如果您在 E2E 上添加我作为朋友、如果您对公开发布代码有任何限制、您可以私下向我发送您的代码。

Unknown 说：

GPIO 以前用作 ePWM、并且工作正常。

这不是 GPIO 的配置吗？有什么问题？
[/报价]
如果您尝试将 GPIO 用作 CLB 的输出、则应将其配置为输出。如果您之前将其用作 ePWM 输出并使用了 SysConfig、那么该工具会为 ePWM 外设配置引脚、并且它会正常工作。 CLB 在这方面不同、因为您将依靠交叉开关将信号从 CLB 路由到 GPIO。因此、GPIO 需要配置为输出。

此外、如果您将 GPIO 多路复用器用作 GPIO 引脚、则在该多路复用器应为4的倍数时将其设置为2 (或设置为0)：

0 admin 1 年多前

TI__Guru**** 2337880 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

对于 GPIO 多路复用器、这里不应该是11 (CLB_OUTPUTXBAR8)吗？

CLB 输出 Xbar 配置如下、当我尝试将 GPIO0配置为输出时、它会显示"资源冲突"(GPIO0/79当前被 myCLB_OUTPUTXBAR0使用)

0 admin 1 年多前

TI__Guru**** 2337880 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

Unknown 说：
因此，需要将 GPIO 配置为输出。

如果我理解正确、您的意思是 GPIO 方向应该配置为输出。

EALLOW；
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1；
GpioCtrlRegs.GPADIR.bit.GPIO1 = 1；
EDIS；

但我认为 GPIO 多路复用器应该是11、而不是0或4 (8/12)

Unknown 说：
此外，如果将 GPIO 多路复用器用作 GPIO 引脚，则将其设置为2，此时该复用器应是4的倍数(或设置为0)：

我尝试了上述配置、仍然没有来自 GPIO0的输出。

然后、我尝试将 CLB_OUT_EN 设置为0x0F、保持相同、GPIO 0为0、而不是1。

Clb1LogicCtrlRegs.CLB_OUT_EN = 0x0F；
Clb1LogicCfgRegs.CLB_MISC_ACCESS_CTRL.bit.BLKEN = 0；//CLB_enableOutputMaskUpdates

0 admin 1 年多前

TI__Guru**** 2337880 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

0 admin 1 年多前

TI__Guru**** 2337880 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

这里显示、GPIO 多路复用器可以通过来自 CLB OUTPUSXBAR 的信号

0 admin 1 年多前

TI__Guru**** 2337880 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Bishlant：

Unknown 说：
接下来的 CLB 输出 XBAR 配置，当我尝试将 GPIO0配置为输出时，它显示"resource conflict"(GPIO0/79当前正在由 myCLB_OUTPUTXBAR0使用)[/QUO]
可以看到、我对 XBAR 如何配置输出存在误解。在初始 POST 中、您有 GPIO 多路复用器(即不与 XBAR 配置设置为2、但要将 GPIO 引脚用作 GPIO、需要将其配置为0、4、8或12。还有一些其他测试可以帮助调试这一点。

尝试单独使用 GPIO0并将其切换为输出、以确保引脚本身没有问题。尝试使用不同的 GPIO 作为 CLB 输出。

请使用该仿真工具验证您的 CLB 是否按预期运行。有关创建 CLB 工具用户指南中 CLB 图的第3.4节的说明。首先确保已按照2.3节中的安装说明进行操作、以便使用适当的工具来查看仿真输出。

创建差动器件生成的代码的详细说明、找出代码更改存在的原因。这意味着不仅要在此处复制和粘贴代码、还要查看端点的代码并找出不同的行。 CLB 有不同的类型、因此根据您从何种器件迁移、应该会有预期的变化。您要从什么器件迁移？

0 admin 1 年多前

TI__Guru**** 2337880 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好、Omer：

对于第1点、我确认 GPIO0在用作 GPIO 输出时工作正常。

使用仿真工具得到的结果是可以的。抱歉、我可能会让您误解、这是 CLB 的一个新设计、我使用系统配置工具设计 CLB 并对设计进行仿真、一切运行良好、然后我将生成的代码(clb_config.c、board.c)"迁移"到我的项目 (这是位字段项目、因此我修改了所有 lib 函数、如 CLB_configOutputLUT (base、 CLB_OUT0、TILE1_CFG_OUTLUT_0)；更改为 Clb1LogicCfgRegs.clb_output_LUT_0.bit.IN0 = 8；

0 admin 1 年多前

TI__Guru**** 2337880 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

我知道现在、我们可以通过私人消息继续讨论、以帮助解决问题。一旦我们确定了其理由，我就会在这里公布这项决议。

0 admin 1 年多前

TI__Guru**** 2337880 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Bishlant：

正如在我们一侧进行的测试、当使用 CLB 输出 XBAR 输出 CLB 的信号时、确实会设置 GPIO、请确保 CLB 模块连接了逻辑块设计和任何初始化代码。将 GPIO 配置为从 CLB 输出信号时没有硬件限制。

C2000™︎ 微控制器（参考译文帖）

C2000™︎ 微控制器（参考译文帖）(Read Only)

[参考译文] TMS320F280039：CLB 似乎不工作