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工具与软件:
我正在尝试生成4个 PWM 信号。 我可以使用的 PWM 模块为 ePWM8、ePWM9、ePWM10和 ePEM11。 我正在尝试将 ePWM8作为主器件、而其他 PWM 将分别由90°、180°和270°从主器件移位。 我在 ePWM9中获得了所需的相移、但 ePWM10和 ePWM11显示了与 ePWM8相同的信号。 我是否应该配置 ePWM7以便同步链正常工作? 我采用100引脚配置、因此 ePWM7的引脚可用于其他某些功能。 我将随查询一起附加正在使用的配置。
EPwm8Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm8Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm8Regs.TBPRD = EPWM_TIMER_TBPRD; // Set timer period EPwm8Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down EPwm8Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm8Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Enable sync EPwm8Regs.TBCTR = 0x0000; // Clear counter EPwm8Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading EPwm8Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM8A on Zero EPwm8Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM8A on event A, up count EPwm8Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM8B on Zero EPwm8Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Clear PWM8B on event B, up count EPwm8Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Period event EPwm8Regs.ETSEL.bit.INTEN = 1; // Enable INT EPwm8Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on First event EPwm8Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm8Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC; EPwm8Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm8Regs.DBRED.bit.DBRED = EPWM_DB; EPwm8Regs.DBFED.bit.DBFED = EPWM_DB; EPwm9Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm9Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm9Regs.TBPRD = EPWM_TIMER_TBPRD; // Set timer period EPwm9Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down EPwm9Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading EPwm9Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm9Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Enable sync EPwm9Regs.TBCTL.bit.PHSDIR = TB_DOWN; EPwm9Regs.TBPHS.bit.TBPHS = EPWM_TIMER_TBPRD/2; // Phase is 90 EPwm9Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM8A on Zero EPwm9Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM8A on event A, up count EPwm9Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM8B on Zero EPwm9Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Clear PWM8B on event B, up count EPwm9Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Period event EPwm9Regs.ETSEL.bit.INTEN = 1; // Enable INT EPwm9Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on First event EPwm9Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm9Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC; EPwm9Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm9Regs.DBRED.bit.DBRED = EPWM_DB; EPwm9Regs.DBFED.bit.DBFED = EPWM_DB; EPwm10Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm10Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm10Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down EPwm10Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading EPwm10Regs.TBCTL.bit.PHSDIR = TB_DOWN; EPwm10Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm10Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Enable sync EPwm10Regs.TBPRD = EPWM_TIMER_TBPRD; // Set timer period EPwm10Regs.TBPHS.bit.TBPHS = EPWM_TIMER_TBPRD; // Phase is 180 EPwm10Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM8A on Zero EPwm10Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM8A on event A, up count EPwm10Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM8B on Zero EPwm10Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Clear PWM8B on event B, up count EPwm10Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Period event EPwm10Regs.ETSEL.bit.INTEN = 1; // Enable INT EPwm10Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on First event EPwm10Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm10Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC; EPwm10Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm10Regs.DBRED.bit.DBRED = EPWM_DB; EPwm10Regs.DBFED.bit.DBFED = EPWM_DB; EPwm11Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm11Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm11Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down EPwm11Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading EPwm11Regs.TBCTL.bit.PHSDIR = TB_UP; EPwm11Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm11Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Enable sync EPwm11Regs.TBPRD = EPWM_TIMER_TBPRD; // Set timer period EPwm11Regs.TBPHS.bit.TBPHS = EPWM_TIMER_TBPRD/2; // Phase is 270 EPwm11Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM8A on Zero EPwm11Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM8A on event A, up count EPwm11Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM8B on Zero EPwm11Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Clear PWM8B on event B, up count EPwm11Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Period event EPwm11Regs.ETSEL.bit.INTEN = 1; // Enable INT EPwm11Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on First event EPwm11Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm11Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC; EPwm11Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm11Regs.DBRED.bit.DBRED = EPWM_DB; EPwm11Regs.DBFED.bit.DBFED = EPWM_DB;
您好!
如 TRM 图中所示、EPWM10和 EPWM11与 EPWM7/8/9在同步方案的不同部分。 但是、EPWM10可以使用 EPWM7同步输出信号作为其同步输入源、并且通过 EPWM10、EPWM11也可以与 EPWM7同步输出信号同步。 在 EPWM10/11上、可以确认您:
请在初始化后的运行时仔细检查这些寄存器值。
此致、
Allison
您好、Allison、
我的问题是是否有必要设置 ePWM7 (即使我没有使用它)来将 ePWM10同步到 ePWM8。 我无法将 ePWM 用于我的工程。 但我试过它,它也不起作用。 此外、我在调试模式下检查了寄存器值、它们看起来是按顺序排列的。 您是否是指 SYNC_SOC_REGS 寄存器的 SYNCSELECT 寄存器? 由于 ePWM10的同步源之一是 ePWM7 SyncOut、是否有必要对其进行设置?
当我按顺序在所有 ePWM 模块上使用软件同步时、我会获得所需的相移。 这是可行的方法吗? 它会在未来造成任何问题吗?
此致、
Murali
您好 Murali、
您是指 SYNC_SOC_REGS 寄存器的 SYNCSELECT 寄存器吗?
SYNCSELECT[EPWM10SYNCIN] 这就是我所说的。 您是否也选择了此选项?
我无法将 ePWM 用于我的项目。
请您澄清一下上述陈述吗?
此致、
Allison
您好、Allison、
[报价 userid="568270" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1473731/tms320f28375d-help-with-phase-shifted-pwm/5659986 #5659986"]我无法将 ePWM 用于我的工程。
请您澄清一下上述陈述吗?
[报价]我是指 ePWM7。 抱歉拼写错误。
选择 SYNCSELECT[EPWM10SYNCIN ]仅解决了配置 ePWM7的问题。 但在我的设计中、ePWM7的引脚配置为 CAN B。 是否有任何其他方法来同步 ePWM8和 ePWM10?
尊敬的 Murali:
具有 EPWM8的 ePWM 同步组与具有 EPWM 9/10/11的组之间的唯一连接是外部同步源或 EPWM7。 如果您无法使用 EPWM7、则可以尝试通过 EXTSYNCOUT XBAR GPIO 路由 EPWM7 SyncOut、该 GPIO 用作 EPWM10/11的外部同步源。 该器件是否符合您的应用需求?
此致、
Allison