[参考译文] TDA4VM：R5F MPU配置

 {
     /* Region 0 configuration: complete 32 bit address space = 4Gbits */
     .regionId         = 0U,
     .enable           = 1U,
     .baseAddr         = 0x0U,
     .size             = CSL_ARM_R5_MPU_REGION_SIZE_4GB,
     .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
     .exeNeverControl  = 1U,
     .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_RD_WR,
     .shareable        = 1U,
     .cacheable        = (uint32_t)FALSE,
     .cachePolicy      = 0U,
     .memAttr          = 0U,
 },

/** \brief  Memory type and cache policies: Strongly-ordered. */
#define CSL_ARM_R5_MEM_ATTR_STRONGLY_ORDERED               ((uint32_t) 0x0U)
/** \brief  Memory type and cache policies: Shareable. */
#define CSL_ARM_R5_MEM_ATTR_SHAREABLE                      ((uint32_t) 0x1U)
/** \brief  Memory type and cache policies:
            Outer and Inner write-through, no write-allocate. */
#define CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA                ((uint32_t) 0x2U)
/** \brief  Memory type and cache policies:
            Outer and Inner write-back, no write-allocate. */
#define CSL_ARM_R5_MEM_ATTR_CACHED_WB_NO_WA                ((uint32_t) 0x3U)
/** \brief  Memory type and cache policies: Non cacheable. */
#define CSL_ARM_R5_MEM_ATTR_STRONGLY_NON_CACHED            ((uint32_t) 0x4U)
/** \brief  Memory type and cache policies:
            Outer and Inner write-back, write-allocate. */
#define CSL_ARM_R5_MEM_ATTR_CACHED_WB_WA                   ((uint32_t) 0x5U)
/** \brief  Memory type and cache policies: Non-shareable Device. */
#define CSL_ARM_R5_MEM_ATTR_NON_SHAREABLE                  ((uint32_t) 0x6U)
/** \brief  This should be passed to configuration. */
#define CSL_ARM_R5_MEM_ATTR_MAX                            ((uint32_t) 0x7U)