例程是单次发送且CPU没有接收中断，在while中连续发送不好使
参考历程ipc_ex2_msgqueue_cm
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您可以看一下 ipc.h内的函数说明
一个是read message,一个是read command
//*****************************************************************************
//
//! Reads a message from the messageQueue.
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance
//! \param addrCorrEnable is the flag used to determine whether or not to
//! convert the addr parameter to remote core's address space
//! \param msg specifies the address of the \e IPC_Message_t instance to which
//! the message needs to be read
//! \param block specifies whether to allow function to block until a message
//! is available in the message queue
//!
//! This function checks if there is a message in the message queue. If so, it
//! reads the message and writes to the address pointed to by \e msg into.
//!
//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE
//! (converts the address to remote core's address space) or
//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter)
//! The \e block parameter can be one of the following values:
//! \b IPC_BLOCKING_CALL or \b IPC_NONBLOCKING_CALL.
//!
//! \return \b false if the queue is empty. \b true if the message successfully
//! read.
//
//*****************************************************************************
extern bool
IPC_readMessageFromQueue(IPC_Type_t ipcType,
volatile IPC_MessageQueue_t *msgQueue,
bool addrCorrEnable, IPC_Message_t *msg, bool block);
//*****************************************************************************
//
//! Reads a command sent by the Remote core
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param flags is the IPC flag mask for the flags sent by the remote core
//! \param addrCorrEnable is the flag used to determine whether or not to
//! convert the addr parameter to remote core's address space
//! \param command is the 32-bit pointer at which the command value is read to
//! \param addr is the 32-bit pointer at which address value is read to
//! \param data is the 32-bit pointer at which the data is read to
//!
//! Allows the caller to read a command sent by the remote core. A command
//! consists of a unique command value, a 32-bit address and a 32-bit data.
//! There may be differences in the address spaces of Local and Remote core.
//! For example in case of F2838X device, the address spaces of C28x core and
//! CM core are different. In case the \e addr refers to an address in the IPC
//! MSG RAM, \e addrCorrEnable param may be used to correct the address mismatch
//!
//! The \e flags parameter can be any of the IPC flag values: \b IPC_FLAG0 -
//! \b IPC_FLAG31.
//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE
//! (converts the address to remote core's address space) or
//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter)
//!
//! \note The application is expected to acknowledge the flag and send a
//! response (if needed) after reading the command
//!
//! \note \e addrCorrEnable parameter must be kept same on the sending and
//! receiving cores
//!
//! \return Returns \b true if the command is read properly and \b false if
//! the designated flags were empty and hence command was not read.
//
//*****************************************************************************
extern bool
IPC_readCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable,
uint32_t *command, uint32_t *addr, uint32_t *data);
CPU如何加接收中断
在英文E2E上有相关讨论，您可以先看一下
https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/891832/ccs-tms320f28388d-how-to-trigger-ipc-interrupt-in-cpu1
https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/852116/tms320f28388d-how-to-trigger-interrupt-by-sending-ipc-message-cm-to-cpu1
若还是不能成功，请您再次回复，并附上代码
//#############################################################################
//
// FILE: ethernet_ipc_ex1_basic_c28x1.c
//
// TITLE: Ethernet IPC example with interrupt
//
//! \addtogroup driver_cm_c28x_dual_example_list
//! <h1> Ethernet + IPC basic message passing example with interrupt </h1>
//!
//! This example demonstrates how to configure IPC and pass information from
//! C28x to CM core without message queues. This configures the Pinmux for Ethernet
//! Prepares the Ethernet frame that is sent to the CM core
//! over IPC Message RAM. Uses the IPC command interface to signal
//! the IPC Command, Packet address, Packet Length which is used by CM
//! side code to send it on the Ethernet Line, which is acknowledged by
//! the CM core side code over IPC on succesfully receiving a packet
//! It is recommended to run the C28x1 core first, followed by the CM core.
//!
//! \b External \b Connections \n
//! - Connections for Ethernet in MII mode
//!
//! \b Watch \b Variables \n
//! - pass
//!
//
//#############################################################################
// $TI Release: F2838x Support Library v3.03.00.00 $
// $Release Date: Sun Oct 4 16:00:36 IST 2020 $
// $Copyright:
// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "driverlib.h"
#include "device.h"
//
// Defines
//
#define IPC_CMD_READ_MEM 0x1001
#define IPC_CMD_RESP 0x2001
#define TEST_PASS 0x5555
#define TEST_FAIL 0xAAAA
#define PACKET_LENGTH 132
#pragma DATA_SECTION(packetData, "MSGRAM_CPU_TO_CM")
uint8_t packetData[PACKET_LENGTH];
uint32_t pass;
uint16_t count,countpr;
uint32_t command, addr, data;
void IPC_ISR0()
{
IPC_readCommand(IPC_CPU1_L_CM_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
&command, &addr, &data);
IPC_ackFlagRtoL(IPC_CPU1_L_CM_R, IPC_FLAG0);
// IPC_sendResponse(IPC_CPU1_L_CM_R, TEST_PASS);
count++;
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP11);
}
//
void main(void)
{
int i;
//
// Initialize device clock and peripherals
//
Device_init();
Interrupt_initModule();
Interrupt_initVectorTable();
//
// Boot CM core
//
#ifdef _FLASH
Device_bootCM(BOOTMODE_BOOT_TO_FLASH_SECTOR0);
#else
Device_bootCM(BOOTMODE_BOOT_TO_S0RAM);
#endif
//
// Clear any IPC flags if set already
//
IPC_clearFlagLtoR(IPC_CPU1_L_CM_R, IPC_FLAG_ALL);
IPC_registerInterrupt(IPC_CPU1_L_CM_R, IPC_INT0, IPC_ISR0);
// Synchronize both the cores.
//
IPC_sync(IPC_CPU1_L_CM_R, IPC_FLAG31);
Interrupt_enable(INT_CMTOCPUXIPC0);
EINT;
ERTM;
//
// Send a message without message queue
// Since C28x and CM does not share the same address space for shared RAM,
// ADDRESS_CORRECTION is enabled
// Length of the data to be read is passed as data.
//
IPC_sendCommand(IPC_CPU1_L_CM_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
IPC_CMD_READ_MEM, (uint32_t)packetData, PACKET_LENGTH);
//
// Wait for acknowledgment
//
// IPC_waitForAck(IPC_CPU1_L_CM_R, IPC_FLAG0);
while(1)
{
if(count!=countpr)
{
countpr = count;
IPC_sendCommand(IPC_CPU1_L_CM_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
IPC_CMD_READ_MEM, (uint32_t)packetData, PACKET_LENGTH);
}
}
}
//
// End of File
//
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "driverlib_cm.h"
//
// Defines
//
#define IPC_CMD_READ_MEM 0x1001
#define IPC_CMD_RESP 0x2001
#define TEST_PASS 0x5555
#define TEST_FAIL 0xAAAA
//
// Defines
//
#define PACKET_LENGTH 132
#define ETHERNET_NO_OF_RX_PACKETS 1U
//
//Change this define for changing Packet buffer length
//
#define ETHERNET_MAX_PACKET_LENGTH 1538U
uint16_t count;
//
// Globals
//
uint8_t pData[PACKET_LENGTH];
uint8_t Ethernet_rxBuffer[ETHERNET_NO_OF_RX_PACKETS *
ETHERNET_MAX_PACKET_LENGTH];
Ethernet_Handle emac_handle;
Ethernet_Pkt_Desc pktDesc;
extern uint32_t Ethernet_rxInterruptCount;
bool status = false;
uint32_t command, addr, data;
// IPC ISR for Flag 0.
// C28x core sends data without message queue using Flag 0
uint8_t packetData[PACKET_LENGTH];
void IPC_ISR0()
{
IPC_readCommand(IPC_CM_L_CPU1_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
&command, &addr, &data);
IPC_sendResponse(IPC_CM_L_CPU1_R, TEST_PASS);
IPC_sendCommand(IPC_CM_L_CPU1_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
IPC_CMD_READ_MEM, (uint32_t)packetData, PACKET_LENGTH);
IPC_ackFlagRtoL(IPC_CM_L_CPU1_R, IPC_FLAG0);
count++;
}
void main(void)
{
//
// Clear any IPC flags if set already
//
IPC_clearFlagLtoR(IPC_CM_L_CPU1_R, IPC_FLAG_ALL);
//
// Enable IPC interrupts
//
IPC_registerInterrupt(IPC_CM_L_CPU1_R, IPC_INT0, IPC_ISR0);
//
// Synchronize both the cores.
//
IPC_sync(IPC_CM_L_CPU1_R, IPC_FLAG31);
//
//The control data to C28x side can be picked up from Ethernet buffer and
//Passed to Ethernet
//
// Send response to C28x core
//
// if(status)
// {
// IPC_sendResponse(IPC_CM_L_CPU1_R, TEST_PASS);
// }
// else
// {
// IPC_sendResponse(IPC_CM_L_CPU1_R, TEST_FAIL);
// }
//
// Acknowledge the flag
//
// IPC_sendCommand(IPC_CM_L_CPU1_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
// IPC_CMD_READ_MEM, (uint32_t)packetData, PACKET_LENGTH);
// __asm(" bkpt #0");
while(1)
{
if(IPC_getResponse(IPC_CM_L_CPU1_R) == TEST_PASS)
{
// IPC_sendCommand(IPC_CM_L_CPU1_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
// IPC_CMD_READ_MEM, (uint32_t)packetData, PACKET_LENGTH);
// count=0;
}
}
}
//
// End of File
//
//#############################################################################
//
// FILE: ethernet_ipc_ex1_basic_c28x1.c
//
// TITLE: Ethernet IPC example with interrupt
//
//! \addtogroup driver_cm_c28x_dual_example_list
//! <h1> Ethernet + IPC basic message passing example with interrupt </h1>
//!
//! This example demonstrates how to configure IPC and pass information from
//! C28x to CM core without message queues. This configures the Pinmux for Ethernet
//! Prepares the Ethernet frame that is sent to the CM core
//! over IPC Message RAM. Uses the IPC command interface to signal
//! the IPC Command, Packet address, Packet Length which is used by CM
//! side code to send it on the Ethernet Line, which is acknowledged by
//! the CM core side code over IPC on succesfully receiving a packet
//! It is recommended to run the C28x1 core first, followed by the CM core.
//!
//! \b External \b Connections \n
//! - Connections for Ethernet in MII mode
//!
//! \b Watch \b Variables \n
//! - pass
//!
//
//#############################################################################
// $TI Release: F2838x Support Library v3.03.00.00 $
// $Release Date: Sun Oct 4 16:00:36 IST 2020 $
// $Copyright:
// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "driverlib.h"
#include "device.h"
//
// Defines
//
#define IPC_CMD_READ_MEM 0x1001
#define IPC_CMD_RESP 0x2001
#define TEST_PASS 0x5555
#define TEST_FAIL 0xAAAA
#define PACKET_LENGTH 132
#pragma DATA_SECTION(packetData, "MSGRAM_CPU_TO_CM")
uint8_t packetData[PACKET_LENGTH];
uint32_t pass;
uint16_t count,countpr;
uint32_t command, addr, data;
void IPC_ISR1()
{
IPC_readCommand(IPC_CPU1_L_CM_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
&command, &addr, &data);
IPC_ackFlagRtoL(IPC_CPU1_L_CM_R, IPC_FLAG0);
// IPC_sendResponse(IPC_CPU1_L_CM_R, TEST_PASS);
count++;
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP11);
}
//
void main(void)
{
int i;
//
// Initialize device clock and peripherals
//
Device_init();
Interrupt_initModule();
Interrupt_initVectorTable();
//
// Boot CM core
//
#ifdef _FLASH
Device_bootCM(BOOTMODE_BOOT_TO_FLASH_SECTOR0);
#else
Device_bootCM(BOOTMODE_BOOT_TO_S0RAM);
#endif
//
// Clear any IPC flags if set already
//
IPC_clearFlagLtoR(IPC_CPU1_L_CM_R, IPC_FLAG_ALL);
IPC_registerInterrupt(IPC_CPU1_L_CM_R, IPC_INT0, IPC_ISR1);
// Synchronize both the cores.
//
IPC_sync(IPC_CPU1_L_CM_R, IPC_FLAG31);
Interrupt_enable(INT_CMTOCPUXIPC0);
EINT;
ERTM;
//
// Send a message without message queue
// Since C28x and CM does not share the same address space for shared RAM,
// ADDRESS_CORRECTION is enabled
// Length of the data to be read is passed as data.
//
IPC_sendCommand(IPC_CPU1_L_CM_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
IPC_CMD_READ_MEM, (uint32_t)packetData, PACKET_LENGTH);
//
// Wait for acknowledgment
//
// IPC_waitForAck(IPC_CPU1_L_CM_R, IPC_FLAG0);
while(1)
{
if(count!=countpr)
{
countpr = count;
IPC_sendCommand(IPC_CPU1_L_CM_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
IPC_CMD_READ_MEM, (uint32_t)packetData, PACKET_LENGTH);
}
}
}
//
// End of File
//
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "driverlib_cm.h"
//
// Defines
//
#define IPC_CMD_READ_MEM 0x1001
#define IPC_CMD_RESP 0x2001
#define TEST_PASS 0x5555
#define TEST_FAIL 0xAAAA
//
// Defines
//
#define PACKET_LENGTH 132
#define ETHERNET_NO_OF_RX_PACKETS 1U
//
//Change this define for changing Packet buffer length
//
#define ETHERNET_MAX_PACKET_LENGTH 1538U
uint16_t count;
//
// Globals
//
uint8_t pData[PACKET_LENGTH];
uint8_t Ethernet_rxBuffer[ETHERNET_NO_OF_RX_PACKETS *
ETHERNET_MAX_PACKET_LENGTH];
Ethernet_Handle emac_handle;
Ethernet_Pkt_Desc pktDesc;
extern uint32_t Ethernet_rxInterruptCount;
bool status = false;
uint32_t command, addr, data;
// IPC ISR for Flag 0.
// C28x core sends data without message queue using Flag 0
uint8_t packetData[PACKET_LENGTH];
void IPC_ISR0()
{
IPC_readCommand(IPC_CM_L_CPU1_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
&command, &addr, &data);
IPC_sendResponse(IPC_CM_L_CPU1_R, TEST_PASS);
IPC_sendCommand(IPC_CM_L_CPU1_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
IPC_CMD_READ_MEM, (uint32_t)packetData, PACKET_LENGTH);
IPC_ackFlagRtoL(IPC_CM_L_CPU1_R, IPC_FLAG0);
count++;
}
void main(void)
{
//
// Clear any IPC flags if set already
//
IPC_clearFlagLtoR(IPC_CM_L_CPU1_R, IPC_FLAG_ALL);
//
// Enable IPC interrupts
//
IPC_registerInterrupt(IPC_CM_L_CPU1_R, IPC_INT0, IPC_ISR0);
//
// Synchronize both the cores.
//
IPC_sync(IPC_CM_L_CPU1_R, IPC_FLAG31);
//
//The control data to C28x side can be picked up from Ethernet buffer and
//Passed to Ethernet
//
// Send response to C28x core
//
// if(status)
// {
// IPC_sendResponse(IPC_CM_L_CPU1_R, TEST_PASS);
// }
// else
// {
// IPC_sendResponse(IPC_CM_L_CPU1_R, TEST_FAIL);
// }
//
// Acknowledge the flag
//
// IPC_sendCommand(IPC_CM_L_CPU1_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
// IPC_CMD_READ_MEM, (uint32_t)packetData, PACKET_LENGTH);
// __asm(" bkpt #0");
while(1)
{
if(IPC_getResponse(IPC_CM_L_CPU1_R) == TEST_PASS)
{
// IPC_sendCommand(IPC_CM_L_CPU1_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE,
// IPC_CMD_READ_MEM, (uint32_t)packetData, PACKET_LENGTH);
// count=0;
}
}
}
//
// End of File
//
CM中 IPC_registerInterrupt(IPC_CM_L_CPU1_R, IPC_INT0, IPC_ISR0);为什么IPC_INT0能进入其他不行，没有看到在何使能中断
1 CM中的代码没有改变
2 CPU1内的代码如下
//#############################################################################
//
// FILE: ipc_ex2_msgqueue_c28x1.c
//
// TITLE: IPC example with interrupt and message queue
//
//! \addtogroup driver_cm_c28x_dual_example_list
//! <h1> IPC message passing example with interrupt and message queue </h1>
//!
//! This example demonstrates how to configure IPC and pass information from
//! C28x to CM core with message queues.
//! It is recommended to run the C28x1 core first, followed by the CM core.
//!
//! \b External \b Connections \n
//! - None.
//!
//! \b Watch \b Variables \n
//! - pass
//!
//
//#############################################################################
// $TI Release: F2838x Support Library v3.03.00.00 $
// $Release Date: Sun Oct 4 16:00:36 IST 2020 $
// $Copyright:
// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "driverlib.h"
#include "device.h"
//
// Defines
//
#define IPC_CMD_READ_MEM 0x1001
#define IPC_CMD_RESP 0x2001
#define TEST_PASS 0x5555
#define TEST_FAIL 0xAAAA
#pragma DATA_SECTION(readData, "MSGRAM_CPU_TO_CM")
uint32_t readData[10];
uint32_t pass;
__interrupt void IPC_ISR1(void);
__interrupt void IPC_ISR1()
{
IPC_MessageQueue_t messageQueue;
IPC_Message_t RxMsg;
//
// Read message from the queue
// Return message from CM does not use the address field, hence
// ADDRESS_COREECTION feature is not used
//
IPC_readMessageFromQueue(IPC_CPU1_L_CM_R, &messageQueue, IPC_ADDR_CORRECTION_DISABLE,
&RxMsg, IPC_BLOCKING_CALL);
if((RxMsg.command == IPC_CMD_RESP) && (RxMsg.dataw1 == TEST_PASS) && (RxMsg.dataw2 == 1))
pass = 1;
else
pass = 0;
//
// Acknowledge the flag
//
IPC_ackFlagRtoL(IPC_CPU1_L_CM_R, IPC_FLAG0);
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP11);
}
//
// Main
//
void main(void)
{
int i;
IPC_MessageQueue_t messageQueue;
IPC_Message_t TxMsg;
//
// Initialize device clock and peripherals
//
Device_init();
//
// Boot CM core
//
#ifdef _FLASH
Device_bootCM(BOOTMODE_BOOT_TO_FLASH_SECTOR0);
#else
Device_bootCM(BOOTMODE_BOOT_TO_S0RAM);
#endif
Interrupt_initModule();
Interrupt_initVectorTable();
// Clear any IPC flags if set already
//
IPC_clearFlagLtoR(IPC_CPU1_L_CM_R, IPC_FLAG_ALL);
//
// Enable IPC interrupts
//
IPC_registerInterrupt(IPC_CPU1_L_CM_R, IPC_INT1, IPC_ISR1);
//
// Clear any IPC flags if set already
//
// IPC_clearFlagLtoR(IPC_CPU1_L_CM_R, IPC_FLAG_ALL);
//
// Initialize message queue
//
IPC_initMessageQueue(IPC_CPU1_L_CM_R, &messageQueue, IPC_INT1, IPC_INT1);
// Synchronize both the cores
//
IPC_sync(IPC_CPU1_L_CM_R, IPC_FLAG31);
EINT;
ERTM;
//
// Fill in the data to be sent
//
for(i=0; i<10; i++)
{
readData[i] = i;
}
//
// Update the message
//
TxMsg.command = IPC_CMD_READ_MEM;
TxMsg.address = (uint32_t)readData;
TxMsg.dataw1 = 10; // Using dataw1 as data length
TxMsg.dataw2 = 1; // Message identifier
//
// Send message to the queue
// Since C28x and CM does not share the same address space for shared RAM,
// ADDRESS_CORRECTION is enabled
//
IPC_sendMessageToQueue(IPC_CPU1_L_CM_R, &messageQueue, IPC_ADDR_CORRECTION_ENABLE,
&TxMsg, IPC_BLOCKING_CALL);
//
// End of example. Loop forever
//
// while(1);
}
//
// End of File
//
