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void CMPSS_Init(Uint16 base1,Uint16 u16DacHigh,Uint16 u16DacLow)
{
// Enable CMPSS1
CMPSS_enableModule(base1);
// Use VDDA as the reference for comparator DACs
CMPSS_configDAC(base1,CMPSS_DACVAL_SYSCLK |CMPSS_DACREF_VDDA |CMPSS_DACSRC_SHDW);
// Set DAC to H and L values
CMPSS_setDACValueHigh(base1, u16DacHigh);
// Make sure the asynchronous path compare high and low event
// does not go to the OR gate with latched digital filter output
// hence no additional parameter CMPSS_OR_ASYNC_OUT_W_FILT is passed
// comparator oputput is "not" inverted for high compare event
CMPSS_configHighComparator(base1, CMPSS_INSRC_DAC);
// Comparator output is inverted for for low compare event
CMPSS_configFilterHigh(base1, 2, 10, 7);
// Reset filter logic & start filtering
CMPSS_initFilterHigh(base1);
// Configure CTRIPOUT path
CMPSS_configOutputsHigh(base1, CMPSS_TRIP_FILTER | CMPSS_TRIPOUT_FILTER);
// Comparator hysteresis control , set to 2x typical value
CMPSS_setHysteresis(base1, 0);
// Clear the latched comparator events
CMPSS_clearFilterLatchHigh(base1);
}
