TMS320F28335: 28335 和FPGA双口RAM 并口通讯 出现读写使能同时拉低?

现在是28335读FPGA的数据：

可以看到XRD和XWE 的同时拉低，但手册里说这两条线是互斥的，所以现在很疑惑出现这个状态！

下面是我Xintf的初始化的代码

void init_zone7(void)
{
    //
    // Make sure the XINTF clock is enabled
    //
    EALLOW;
    SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1;
    EDIS;

    //
    // Configure the GPIO for XINTF with a 16-bit data bus
    // This function is in DSP2833x_Xintf.c
    //
    InitXintf16Gpio();

    EALLOW;

    //
    // All Zones
    // Timing for all zones based on XTIMCLK = SYSCLKOUT/2
    //
    XintfRegs.XINTCNF2.bit.XTIMCLK = 1;

    //
    // Buffer up to 0 writes
    //
    XintfRegs.XINTCNF2.bit.WRBUFF = 0;

    //
    // XCLKOUT is enabled
    //
    XintfRegs.XINTCNF2.bit.CLKOFF = 0;

    //
    // XCLKOUT = XTIMCLK
    //
    XintfRegs.XINTCNF2.bit.CLKMODE = 0;

    //
    // Enable XHOLD to prevent XINTF bus from going into high impedance state
    // whenever TZ3 signal goes low. This occurs because TZ3 on GPIO14 is
    // shared with HOLD of XINTF
    //
    XintfRegs.XINTCNF2.bit.HOLD =   1;

    //
    // Zone 7
    // When using ready, ACTIVE must be 1 or greater. Lead must always be 1 or
    // greater. Zone write timing
    //
    XintfRegs.XTIMING7.bit.XWRLEAD = 2;
    XintfRegs.XTIMING7.bit.XWRACTIVE = 4;
    XintfRegs.XTIMING7.bit.XWRTRAIL = 2;

    //
    // Zone read timing
    //
    XintfRegs.XTIMING7.bit.XRDLEAD = 2;
    XintfRegs.XTIMING7.bit.XRDACTIVE = 6;
    XintfRegs.XTIMING7.bit.XRDTRAIL = 0;

    //
    // don't double all Zone read/write lead/active/trail timing
    //
    XintfRegs.XTIMING7.bit.X2TIMING = 1;

    //
    // Zone will  sample XREADY signal
    //
    XintfRegs.XTIMING7.bit.USEREADY = 1;
    XintfRegs.XTIMING7.bit.READYMODE = 0;

    //
    // 1,1 = x16 data bus
    // 0,1 = x32 data bus
    // other values are reserved
    //
    XintfRegs.XTIMING7.bit.XSIZE = 3;

    // Bank switching
    // Assume Zone 7 is slow, so add additional BCYC cycles
    // when ever switching from Zone 7 to another Zone.
    // This will help avoid bus contention.
    XintfRegs.XBANK.bit.BANK = 7;
    XintfRegs.XBANK.bit.BCYC = 7;
    EDIS;
//
//    //
//    // Force a pipeline flush to ensure that the write to
//    // the last register configured occurs before returning.
//    //
//    __asm(" RPT #7 || NOP");
}

下面是我读数据的代码

for ( i = 0; i < 2048; i++)
{
    /* code */
    *(DSP_Buf+i) = *(FPGA_RamStart+i);
}