main函数：
void main(void)
{
Uint16 cmd=0xfcbc;
sInitialDSP();
Flash_API_Write_to_Flash((Uint16 *) 0x3F0006,&cmd,1);
}
sInitialDSP:
void sInitialDSP(void)
{
// Step 1. Initialize System Control registers, PLL, WatchDog, Clocks to default state:
sInitSysCtrl();
MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
EALLOW;
Flash_CPUScaleFactor = SCALE_FACTOR;
EDIS;
EALLOW;
Flash_CallbackPtr = &Flash_API_CallbackFunction;
EDIS;
Flash_API_CallbackCounter = 0;
sInitFlash();
}
sInitSysCtrl:
void sInitSysCtrl(void)
{
//0----The TBCLK (Time Base Clock) within each enabled ePWM module is stopped. (default). If, however,
//the ePWM clock enable bit is set in the PCLKCR1 register, then the ePWM module will still be
//clocked by SYSCLKOUT even if TBCLKSYNC is 0.
//1----All enabled ePWM module clocks are started with the first rising edge of TBCLK aligned. For perfectly
//synchronized TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must be set
//identically. The proper procedure for enabling ePWM clocks is as follows:
//1. Enable ePWM module clocks in the PCLKCR1 register.
//2. Set TBCLKSYNC to 0.
//3. Configure prescaler values and ePWM modes.
//4. Set TBCLKSYNC to 1.
//Disable watchdog module
EALLOW;
SysCtrlRegs.WDCR = 0x0068;
EDIS;
//
// DINT; // Global Disable all Interrupts
// IER = 0x0000; // Disable CPU interrupts
// IFR = 0x0000; // Clear all CPU interrupt flags
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // Enable ADC peripheral clock
(*Device_cal)();
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 0; // Return ADC clock to original state
EDIS;
// This function switches to External CRYSTAL oscillator and turns off all other clock
// sources to minimize power consumption. This option may not be available on all
// device packages
EALLOW;
SysCtrlRegs.CLKCTL.bit.INTOSC1OFF = 0;
SysCtrlRegs.CLKCTL.bit.OSCCLKSRCSEL=0; // Clk Src = INTOSC1
SysCtrlRegs.CLKCTL.bit.XCLKINOFF=1; // Turn off XCLKIN
SysCtrlRegs.CLKCTL.bit.XTALOSCOFF=1; // Turn off XTALOSC
SysCtrlRegs.CLKCTL.bit.INTOSC2OFF=1; // Turn off INTOSC2
EDIS;
// Initialize the PLL control: PLLCR and CLKINDIV
// Make sure the PLL is not running in limp mode
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
{
EALLOW;
// OSCCLKSRC1 failure detected. PLL running in limp mode.
// Re-enable missing clock logic.
SysCtrlRegs.PLLSTS.bit.MCLKCLR = 1;
EDIS;
// Replace this line with a call to an appropriate
// SystemShutdown(); function.
__asm(" ESTOP0"); // Uncomment for debugging purposes
}
// DIVSEL MUST be 0 before PLLCR can be changed from
// 0x0000. It is set to 0 by an external reset XRSn
if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
EDIS;
}
if (SysCtrlRegs.PLLCR.bit.DIV != 18)
{
EALLOW;
// Before setting PLLCR turn off missing clock detect logic
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
SysCtrlRegs.PLLCR.bit.DIV = 18;
EDIS;
// Optional: Wait for PLL to lock.
// During this time the CPU will switch to OSCCLK/2 until
// the PLL is stable. Once the PLL is stable the CPU will
// switch to the new PLL value.
//
// This time-to-lock is monitored by a PLL lock counter.
//
// Code is not required to sit and wait for the PLL to lock.
// However, if the code does anything that is timing critical,
// and requires the correct clock be locked, then it is best to
// wait until this switching has completed.
// Wait for the PLL lock bit to be set.
// The watchdog should be disabled before this loop, or fed within
// the loop via ServiceDog().
// Uncomment to disable the watchdog
EALLOW;
// Disable watchdog module
SysCtrlRegs.WDCR = 0x0068;
EDIS;
while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
{
// Uncomment to service the watchdog
// ServiceDog();
}
EALLOW;
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
EDIS;
}
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
EDIS;
// Initialize the peripheral clocks
// SysCtrlRegs.HISPCP.all = 0x0000; //SYSCLKOUT/1 (ADC,)
EALLOW;
//
// LOSPCP prescale register settings, normally it will be set to default
// values
//
//
//GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // GPIO18 = XCLKOUT
//
SysCtrlRegs.LOSPCP.all = 0x0002;
//
// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT
//
SysCtrlRegs.XCLK.bit.XCLKOUTDIV=2;
//
// Peripheral clock enables set for the selected peripherals.
// If you are not using a peripheral leave the clock off
// to save on power.
//
// Note: not all peripherals are available on all F2806x derivates.
// Refer to the datasheet for your particular device.
//
// This function is not written to be an example of efficient code.
//
SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
SysCtrlRegs.PCLKCR1.bit.EPWM7ENCLK = 1; // ePWM7
SysCtrlRegs.PCLKCR1.bit.EPWM8ENCLK = 1; // ePWM8
SysCtrlRegs.PCLKCR0.bit.HRPWMENCLK = 1; // HRPWM
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1
SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2
SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1
SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2
SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3
SysCtrlRegs.PCLKCR2.bit.HRCAP1ENCLK = 1; // HRCAP1
SysCtrlRegs.PCLKCR2.bit.HRCAP2ENCLK = 1; // HRCAP2
SysCtrlRegs.PCLKCR2.bit.HRCAP3ENCLK = 1; // HRCAP3
SysCtrlRegs.PCLKCR2.bit.HRCAP4ENCLK = 1; // HRCAP4
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
SysCtrlRegs.PCLKCR3.bit.COMP1ENCLK = 1; // COMP1
SysCtrlRegs.PCLKCR3.bit.COMP2ENCLK = 1; // COMP2
SysCtrlRegs.PCLKCR3.bit.COMP3ENCLK = 1; // COMP3
SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2
SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA
SysCtrlRegs.PCLKCR3.bit.CLA1ENCLK = 1; // CLA1
SysCtrlRegs.PCLKCR3.bit.USB0ENCLK = 1; // USB0
SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C-A
SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A
SysCtrlRegs.PCLKCR0.bit.SPIBENCLK = 1; // SPI-B
SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A
SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B
SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A
SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
EDIS;
}
sInitFlash:
void sInitFlash(void)
{
EALLOW;
//Enable Flash Pipeline mode to improve performance
//of code executed from Flash.
FlashRegs.FOPT.bit.ENPIPE = 1;
// CAUTION
//Minimum waitstates required for the flash operating
//at a given CPU rate must be characterized by TI.
//Refer to the datasheet for the latest information.
//Set the Paged Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;
//Set the Random Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;
//Set the Waitstate for the OTP
FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;
// CAUTION
//ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED
FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");
}
