TMS320F280025: 关于设计硬件过流保护时TZ模块与DC模块的相关问题

谢谢Li总又一次为我答疑解惑，你的意思是说DCAEVT1的相关输出会使OST跳闸，FLAG.DCAEVT1并不会置1对吗？我会认真看看你所说的例程的，感谢！

也就是说DCAEVT1如果触发了中断，会使FLAG.OST置1，FLAG.DCAEVT1并不会置1对吗？

好的Li总 我再试试吧 您看我现在的配置有问题吗？我确实有点找不到哪里出问题了 现在FLAG.DCAEVT1不置1，只有FLAG.OST1置1

Li总 只用DCAEVT1可以触发中断吗？因为我看到你画橙色圈的DCAEVT1信号并没有进入OST event模块呀

好的 我现在上传的就是从CMPSS开始的全部了 但是完整工程文件被加密了我传不了T T 您看这些够吗，其他功能我都不用动 光改这里。

    EALLOW;

    Cmpss3Regs.COMPCTL.bit.COMPDACE = 1;        //比较器DAC使能
    Cmpss3Regs.COMPCTL.bit.COMPHSOURCE = 0;     //高侧比较器方向输入端为DAC
    Cmpss3Regs.COMPCTL.bit.COMPHINV = 0;        //比较器输出不反相
    Cmpss3Regs.COMPCTL.bit.ASYNCHEN = 0;        // 异步比较器输出不馈入OR门与锁存数字滤波器输出

    Cmpss3Regs.COMPDACCTL.bit.DACSOURCE = 0;    //DAC更新数据来自于其影子寄存器
    Cmpss3Regs.COMPDACCTL.bit.SELREF = 0;       //VDDA作为DAC的参考电压:2.5?
    Cmpss3Regs.COMPDACCTL.bit.SWLOADSEL = 0;    //使用系统时钟同步DAC

    Cmpss3Regs.DACHVALS.bit.DACVAL = 434;      //配置DAC的影子寄存器值

        /*数字滤波*///输出不馈入滤波还配置滤波器干啥
    Cmpss3Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 0x3FF;
    Cmpss3Regs.CTRIPHFILCTL.bit.SAMPWIN = 31;
    Cmpss3Regs.CTRIPHFILCTL.bit.THRESH = 31;
    Cmpss3Regs.CTRIPHFILCTL.bit.FILINIT = 1;

    //输出端
    //Cmpss3Regs.COMPCTL.bit.CTRIPOUTHSEL = 0;
    Cmpss3Regs.COMPCTL.bit.CTRIPHSEL = 0;       //比较器输出非同步非滤波信号

    //Cmpss3Regs.COMPHYSCTL.bit.COMPHYS = 4;      //设置典型的滞环宽度

    EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX4 = 0; // MUX4=0  CMPSS3.CTRIPH
    EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX4 = 1;   //复用开关使能
    EPwmXbarRegs.TRIPOUTINV.bit.TRIP4 = 0;
    //CMP3HP输入信号
    AnalogSubsysRegs.CMPHPMXSEL.bit.CMP3HPMXSEL = 1; //选择C2引脚作为高侧比较器3的同向输入端
    
    Cmpss3Regs.DACHVALS.bit.DACVAL= i32temp;//CMPSS3 输入电流 350A触发过载保护
 //DC Init   
    EPwm1Regs.DCAHTRIPSEL.bit.TRIPINPUT4 = 1;//输入
    EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3;//Digital Compare A High Input Select Bits Trip4
    EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 2;//Digital Compare Output A1
    EPwm1Regs.DCACTL.bit.EVT1SRCSEL = 0;//DCAEVT1 Source Signal Select
    EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1;//DCAEVT1 Force Synchronization Signal Select 异步
    EPwm1Regs.DCACTL.bit.EVT1SOCE = 0;//断soc使能
    EPwm1Regs.DCACTL.bit.EVT1SYNCE = 0;//断sync使能
    EPwm1Regs.DCACTL.bit.EVT1LATSEL = 0;//DCAEVT1事件触发时立即更新事件标志，不会延迟。
    
//TZ Init
    EPwm1Regs.TZSEL.all = 0;
    EPwm1Regs.TZFRC.bit.OST = 1;//3kW初始化时处于封波状态
    EPwm1Regs.TZCTL.bit.TZA = 2;
    EPwm1Regs.TZCTL.bit.TZB = 2;
    EPwm1Regs.TZCTL.bit.DCAEVT1 = 2;
    EPwm1Regs.TZSEL.bit.DCAEVT1 = 1;
    EPwm1Regs.TZCTL2.bit.ETZE = 0;
    
EDIS;

ADC接收也是正常的

TZ之前的TB CC DB AQ PC 都是以前别人配置的 我也不太敢动。 

其中 C_INIT_PRD = 6250           

PWM_CLK_DIV = 0             

C_MAX_DB = 320    

gADC.DelayApply为ADC采样延时时间(PWM定时器周期单位）

   //Set the Time-Base (TB) Module
        EPwm1Regs.TBPRD = C_INIT_PRD;//100MHz/2*TBPRD=8k
        EPwm1Regs.CMPB.bit.CMPB = EPwm1Regs.TBPRD - gADC.DelayApply;
        EPwm1Regs.TBPHS.all = 0;
        EPwm1Regs.TBCTL.all = 0xE012;//0xE012 up-down counts
        EPwm1Regs.TBCTL.bit.HSPCLKDIV = PWM_CLK_DIV;
        
    //Set the Counter-compare (CC) Module
        EPwm1Regs.CMPCTL.all = 0x0100;
        EPwm1Regs.CMPA.bit.CMPA = C_INIT_PRD/2;
        
    //Set the Action-qualifier (AQ) Module
        EPwm1Regs.AQCTLA.all = 0x0060;                //From 0x0090  lxt 2015.8.17
        
    //Set the Dead-Band Generator (DB) Module
        EPwm1Regs.AQSFRC.all  = 0x0;
        EPwm1Regs.AQCSFRC.all = 0x0;//0x05; ////BYCAO FOR POWER HAVE PWM OUTPUT
        EPwm1Regs.DBCTL.all = 0x000B;
        EPwm1Regs.DBFED.bit.DBFED = C_MAX_DB;
        EPwm1Regs.DBRED.bit.DBRED = C_MAX_DB;