TMS320F280049C: CLA内存配置问题

user6223372

Part Number: TMS320F280049C
Other Parts Discussed in Thread: SYSCONFIG, C2000WARE

我在sysconfig tool中将RAMLS3配置为共享区域，将RAMLS4配置为CLA程序区域，其余LS区域配置为CPU区域，生成的board.c相关程序如下：

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//*****************************************************************************
//
// CLA Configurations
//
//*****************************************************************************
void myCLA0_init(){
    //
    // Configure all CLA task vectors
    // On Type-1 and Type-2 CLAs the MVECT registers accept full 16-bit task addresses as
    // opposed to offsets used on older Type-0 CLAs
    //
#pragma diag_suppress=770
    //
    // CLA Task 1
    //
    CLA_mapTaskVector(myCLA0_BASE, CLA_MVECT_1, (uint16_t)&Cla1Task1);
    CLA_setTriggerSource(CLA_TASK_1, CLA_TRIGGER_SOFTWARE);
#pragma diag_warning=770
    //
    // Enable the IACK instruction to start a task on CLA in software
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

//*****************************************************************************
//
// CLA Configurations
//
//*****************************************************************************

void myCLA0_init(){
	//
    // Configure all CLA task vectors
    // On Type-1 and Type-2 CLAs the MVECT registers accept full 16-bit task addresses as
    // opposed to offsets used on older Type-0 CLAs
    //
#pragma diag_suppress=770
    //
    // CLA Task 1
    //
    CLA_mapTaskVector(myCLA0_BASE, CLA_MVECT_1, (uint16_t)&Cla1Task1);
    CLA_setTriggerSource(CLA_TASK_1, CLA_TRIGGER_SOFTWARE);
#pragma diag_warning=770
	//
    // Enable the IACK instruction to start a task on CLA in software
    // for all  8 CLA tasks. Also, globally enable all 8 tasks (or a
    // subset of tasks) by writing to their respective bits in the
    // MIER register
    //
	CLA_enableIACK(myCLA0_BASE);
    CLA_enableTasks(myCLA0_BASE, CLA_TASKFLAG_1 );
}


void CLA_init()
{
#ifdef _FLASH
#ifndef CMDTOOL // Linker command tool is not used

    extern uint32_t Cla1ProgRunStart, Cla1ProgLoadStart, Cla1ProgLoadSize;
    extern uint32_t Cla1ConstRunStart, Cla1ConstLoadStart, Cla1ConstLoadSize;

    //
    // Copy the program and constants from FLASH to RAM before configuring
    // the CLA
    //
    memcpy((uint32_t *)&Cla1ProgRunStart, (uint32_t *)&Cla1ProgLoadStart,
           (uint32_t)&Cla1ProgLoadSize);
    memcpy((uint32_t *)&Cla1ConstRunStart, (uint32_t *)&Cla1ConstLoadStart,
        (uint32_t)&Cla1ConstLoadSize );


#endif //CMDTOOL
#endif //_FLASH

	myCLA0_init();
}

//*****************************************************************************
//
// MEMCFG Configurations
//
//*****************************************************************************
void MEMCFG_init(){
	//
	// Initialize RAMs
	//
	MemCfg_initSections(MEMCFG_SECT_MSGCPUTOCLA1);
	MemCfg_initSections(MEMCFG_SECT_MSGCLA1TOCPU);
	while(!MemCfg_getInitStatus(MEMCFG_SECT_MSGCPUTOCLA1));
	while(!MemCfg_getInitStatus(MEMCFG_SECT_MSGCLA1TOCPU));
	//
	// Configure LSRAMs
	//
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS0, MEMCFG_LSRAMCONTROLLER_CPU_ONLY);
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS1, MEMCFG_LSRAMCONTROLLER_CPU_ONLY);
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS2, MEMCFG_LSRAMCONTROLLER_CPU_ONLY);
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS3, MEMCFG_LSRAMCONTROLLER_CPU_CLA1);
	MemCfg_setCLAMemType(MEMCFG_SECT_LS3, MEMCFG_CLA_MEM_DATA);
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS4, MEMCFG_LSRAMCONTROLLER_CPU_CLA1);
	MemCfg_setCLAMemType(MEMCFG_SECT_LS4, MEMCFG_CLA_MEM_PROGRAM);
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS5, MEMCFG_LSRAMCONTROLLER_CPU_ONLY);
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS6, MEMCFG_LSRAMCONTROLLER_CPU_ONLY);
	MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS7, MEMCFG_LSRAMCONTROLLER_CPU_ONLY);
	//
	// Configure GSRAMs
	//
	//
	// Configure Access Protection for RAMs
	//
	MemCfg_setProtection(MEMCFG_SECT_LS0, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_LS1, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_LS2, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_LS3, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_LS4, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_LS5, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_LS6, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_LS7, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS0, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS1, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS2, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	MemCfg_setProtection(MEMCFG_SECT_GS3, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE);
	//
	// Lock/Commit Registers
	//
	//
	// Enable Access Violation Interrupt
	//
	//
	// Correctable error Interrupt
	//
	MemCfg_setCorrErrorThreshold(0);
	MemCfg_disableCorrErrorInterrupt(MEMCFG_CERR_CPUREAD);
}

CMD文件如下：

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CLA_SCRATCHPAD_SIZE = 0x100;
MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to Flash" bootloader mode   */
   BEGIN            : origin = 0x080000, length = 0x000002
   RAMM0            : origin = 0x0000F6, length = 0x00030A
   RAMLS02          : origin = 0x008000, length = 0x001800
//   RAMLS0             : origin = 0x008000, length = 0x000800
//   RAMLS1             : origin = 0x008800, length = 0x000800
//   RAMLS2             : origin = 0x009000, length = 0x000800
   RAMLS3           : origin = 0x009800, length = 0x000800
   RAMLS4           : origin = 0x00A000, length = 0x000800
   RAMLS5           : origin = 0x00A800, length = 0x000800
   RESET            : origin = 0x3FFFC0, length = 0x000002
   /* Flash sectors */
   /* BANK 0 */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

CLA_SCRATCHPAD_SIZE = 0x100;

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x0000F6, length = 0x00030A

   RAMLS02        	: origin = 0x008000, length = 0x001800
//   RAMLS0          	: origin = 0x008000, length = 0x000800
//   RAMLS1          	: origin = 0x008800, length = 0x000800
//   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMLS5      		: origin = 0x00A800, length = 0x000800
   RESET           	: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   /* BANK 0 */
   FLASH_BANK0_SEC0  : origin = 0x080002, length = 0x000FFE	/* on-chip Flash */
//   FLASH_BANK0_SEC1  : origin = 0x081000, length = 0x001000	/* on-chip Flash */
//   FLASH_BANK0_SEC2  : origin = 0x082000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC123 : origin = 0x081000, length = 0x003000	/* on-chip Flash */
//   FLASH_BANK0_SEC3  : origin = 0x083000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC4  : origin = 0x084000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC5  : origin = 0x085000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC6  : origin = 0x086000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC7  : origin = 0x087000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC8  : origin = 0x088000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC9  : origin = 0x089000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000	/* on-chip Flash */

   /* BANK 1 */
   FLASH_BANK1_SEC0  : origin = 0x090000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC1  : origin = 0x091000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC2  : origin = 0x092000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC3  : origin = 0x093000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC4  : origin = 0x094000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC5  : origin = 0x095000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC6  : origin = 0x096000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC7  : origin = 0x097000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC8  : origin = 0x098000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC9  : origin = 0x099000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000	/* on-chip Flash */
   FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0	/* on-chip Flash */

//   FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010  /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x0000F1     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */


   RAMLS6      : origin = 0x00B000, length = 0x000800
   RAMLS7      : origin = 0x00B800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x002000
//   RAMGS1      : origin = 0x00E000, length = 0x002000
//   RAMGS2      : origin = 0x010000, length = 0x002000
   DataRam     : origin = 0x00E000, length = 0x004000
   RAMGS3      : origin = 0x012000, length = 0x001FF8

   CLA1_MSGRAMLOW   : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH  : origin = 0x001500, length = 0x000080

//   RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
}


SECTIONS
{
   codestart        : > BEGIN,     PAGE = 0, ALIGN(4)
   .text            : >> FLASH_BANK0_SEC4 | FLASH_BANK0_SEC5 | FLASH_BANK0_SEC6 | FLASH_BANK0_SEC7,   PAGE = 0, ALIGN(4)
   .cinit           : > FLASH_BANK0_SEC123,     PAGE = 0, ALIGN(4)
   .switch          : > FLASH_BANK0_SEC123,     PAGE = 0, ALIGN(4)
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMM1,     PAGE = 1

   .paratable		: > FLASH_BANK0_SEC15,	PAGE = 0

#if defined(__TI_EABI__)
   .init_array      : > FLASH_BANK0_SEC1,       PAGE = 0,       ALIGN(4)
   .bss             : > RAMLS5,       PAGE = 1
   .bss:output      : > RAMLS02,       PAGE = 0
   .bss:cio         : > RAMLS02,       PAGE = 0
   .data            : > RAMLS5,       PAGE = 1
   .sysmem          : > RAMLS5,       PAGE = 1
   /* Initalized sections go in Flash */
   .const           : > FLASH_BANK0_SEC6,       PAGE = 0,       ALIGN(4)
#else
   .pinit           : > FLASH_BANK0_SEC123,       PAGE = 0,       ALIGN(4)
   .ebss            : >> RAMLS6 | RAMLS7 | RAMGS0,       PAGE = 1
   .esysmem         : > RAMLS5,       PAGE = 0
   .cio             : > RAMLS02,       PAGE = 0
   .econst          : > FLASH_BANK0_SEC6,    PAGE = 0, ALIGN(4)
#endif

   ramgs0           : > RAMGS0,    PAGE = 1
//   ramgs1           : > RAMGS1,    PAGE = 1

   DmaRecvBufFile	: > RAMGS3,    PAGE = 1
   databuf          : > DataRam    PAGE = 1

/********************CLA************************/
#if defined(__TI_EABI__)
    /* CLA specific sections */
    Cla1Prog        : LOAD = FLASH_BANK0_SEC10,
                      RUN = RAMLS4,
                      LOAD_START(Cla1ProgLoadStart),
                      RUN_START(Cla1ProgRunStart),
                      LOAD_SIZE(Cla1ProgLoadSize),
                      PAGE = 0, ALIGN(4)
#else
    /* CLA specific sections */
    Cla1Prog        : LOAD = FLASH_BANK0_SEC10,
                      RUN = RAMLS4,
                      LOAD_START(_Cla1ProgLoadStart),
                      RUN_START(_Cla1ProgRunStart),
                      LOAD_SIZE(_Cla1ProgLoadSize),
                      PAGE = 0, ALIGN(4)
#endif


    Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
    CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1
/************************************************/


#if defined(__TI_EABI__)
   .TI.ramfunc      : LOAD = FLASH_BANK0_SEC123,
                      RUN = RAMLS02,
                      LOAD_START(RamfuncsLoadStart),
                      LOAD_SIZE(RamfuncsLoadSize),
                      LOAD_END(RamfuncsLoadEnd),
                      RUN_START(RamfuncsRunStart),
                      RUN_SIZE(RamfuncsRunSize),
                      RUN_END(RamfuncsRunEnd),
                      PAGE = 0, ALIGN(4)
#else
   GROUP
   {
       .TI.ramfunc
       { -l F021_API_F28004x_FPU32.lib}

   } LOAD = FLASH_BANK0_SEC123,
     RUN = RAMLS02,
     LOAD_START(_RamfuncsLoadStart),
     LOAD_SIZE(_RamfuncsLoadSize),
     LOAD_END(_RamfuncsLoadEnd),
     RUN_START(_RamfuncsRunStart),
     RUN_SIZE(_RamfuncsRunSize),
     RUN_END(_RamfuncsRunEnd),
     PAGE = 0, ALIGN(4)
#endif

/********************CLA************************/
	CLAscratch		:
					{ *.obj(CLAscratch)
					. += CLA_SCRATCHPAD_SIZE;
					*.obj(CLAscratch_end) } >  RAMLS3,	PAGE = 0

   .scratchpad      : > RAMLS3,           PAGE = 0
   .bss_cla         : > RAMLS3,           PAGE = 0

   Cla1DataRam      : > RAMLS3,           PAGE = 0
   cla_shared       : > RAMLS3,           PAGE = 0
   CLADataLS1       : > RAMLS3,           PAGE = 0

#if defined(__TI_EABI__)
   .const_cla      : LOAD = FLASH_BANK0_SEC10,
                      RUN = RAMLS3,
                      RUN_START(Cla1ConstRunStart),
                      LOAD_START(Cla1ConstLoadStart),
                      LOAD_SIZE(Cla1ConstLoadSize),
                      PAGE = 0, ALIGN(4)
#else
   .const_cla      : LOAD = FLASH_BANK0_SEC10,
                      RUN = RAMLS3,
                      RUN_START(_Cla1ConstRunStart),
                      LOAD_START(_Cla1ConstLoadStart),
                      LOAD_SIZE(_Cla1ConstLoadSize),
                      PAGE = 0, ALIGN(4)
#endif
	CLA1mathTables : 	LOAD = FLASH_BANK0_SEC10,
						RUN = RAMLS3,
						LOAD_START(_Cla1TablesLoadStart),
						LOAD_END(_Cla1TablesLoadEnd),
						RUN_START(_Cla1TablesRunStart),
						PAGE = 0
/************************************************/
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

在程序中，定义了结构体strVoltPiCtrl，并将其放到了“CLADataLS1”中，同时在100kHz的PWM中断中使用软件触发的形式触发CLAtask1，

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CLA_forceTasks(myCLA0_BASE,CLA_TASKFLAG_1);
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

CLA_forceTasks(myCLA0_BASE,CLA_TASKFLAG_1);

并试图在PWM中断中对结构体的某些值进行修改，并在CLA中通过这些值进行进一步的计算，并将结果幅值给结构体中的另外一些元素

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#pragma DATA_SECTION(strVoltPiCtrl,"CLADataLS1");
PI_CTRL_MODULE strVoltPiCtrl;
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

#pragma DATA_SECTION(strVoltPiCtrl,"CLADataLS1");
PI_CTRL_MODULE strVoltPiCtrl;

结果在进行Debug时，发现结构体strVoltPiCtrl所处的内存区域为Program区域

导致在Debug模式下，必须先手动connect CLA核，整体程序才能运行，若将程序烧写到Flash，则整体程序将无法运行

经过测试，将100kHz中断中的软件触发CLA屏蔽，或者将PWM中断中屏蔽与该结构体相关的语句，再将程序烧写到FLASH后，则程序又能正常运行，

请问：1.为什么结构体所对应的内存区域为program区域；2.程序为何无法正常运行

4 个月前

0 user6223372 4 个月前

Prodigy 20 points

另外，使用Debug模式，connect CLA核及load symbol后，在Expressions窗口所监视的变量值均是0，但在CPU核的监视窗口则变量均有变换。监视的变量均已放在message内存区域以及CPU和CLA共享的LS内存区域

0 Lydia 4 个月前回复 user6223372

TI__Mastermind 20765 points

您好，

看起来您的 CLAdataLS1部分已分配给链接器 cmd 文件中的 RAMLS3存储器范围。这是故意的吗？ LSRAM3从地址0x009800开始、长度为0x000800、因此如果 strVoltPiCtrl 的长度为0x009900、则这是正常现象、因为它处于该值范围内。是否尝试让 strVoltPiCtrl 成为 CPU 和 CLA 之间的共享变量？如果是、您是否有一个头文件的 strVoltPiCtrl 变量的外部文件在.cla 文件和 main.c 文件中都包含#include？

0 user6223372 4 个月前回复 Lydia

Prodigy 20 points

但是我已经在内存配置时将RAMLS3配置成了MEMCFG_CLA_MEM_DATA，那么这一块区域不应该就是CLA和CPU之间的共享数据内存区域了吗。另外， .cla文件和对应的.c文件都#include了相关的外部变量

0 Lydia 4 个月前回复 user6223372

TI__Mastermind 20765 points

您好，

我有点困惑。您是否希望strVoltPiCtrl被放置在LS4中，因为它专用于程序存储器？以下是您选择的sysconfig MEMCFG，是否正确？或者我是否已切换LSRAM3和LSRAM4？

如果希望CPU和CLA都具有strVoltPiCtrl变量的写入访问权限，则需要将其分配给与具有共享访问权限的LSRAM相关的输出部分。 #pragma将告诉编译器将符号放在您指定的输出部分，无论它是否具有共享内存权限。

我建议尝试尽可能少地修改C2000ware中给出的链接程序cmd文件，以避免出现问题。

C2000 微控制器

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TMS320F280049C: CLA内存配置问题