MSP430FR2433: compare witn the data in FRAM with the data in RAM

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#include <msp430.h>
#include <stdint.h>
#include <string.h>
#include <CJ7100.h>
#include <cmd_process.h>
#include <stdio.h>

/*uint8_t Change_ID = 0x1C;*/
//"stdio.h"和"string.h"
#pragma NOINIT(Change_ID)
uint8_t Change_ID;

#pragma NOINIT(flag)
unsigned long flag[2];

#pragma NOINIT(FRAM_write)
uint8_t FRAM_write[0x800];
//uint8_t FRAM_write_RAM[0x800];   //调用RAM数据进行比较就可以直接比较

uint8_t RD_NG[8]={0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};  //ADRESS: RAM

uint8_t i,printer_ID = 0x01,returndata[6]={0xfc,0x05,0xfc,0x01,0xff,0xff};

int I2Ccount_RX,I2Ccount_TX;
uint16_t address;
uint8_t I2CRXData[100] = {0x00};                    // I2C RX data buffer

#pragma NOINIT(Write_flag)
User_Write Write_flag;

void Init_MCU(void);
void Init_CLOCKS(void);
void Init_UART(void);
void Send_Char(uint8_t dat);
void Send_string(uint8_t *ptr);

uint8_t  test_flag=10;                //=0: 7100与430上电后成功通讯
uint8_t  rxflag=0,txflag=0;
uint8_t  rxcount=0,txcount=0;
uint8_t  rxbuff[100];
uint8_t  txbuff[100];

uint16_t SYSCFG0_copy;

int main(void)
{
    int i,j;
    char dat_test;
    WDTCTL = WDTPW | WDTHOLD;   // stop watchdog timer
    Init_MCU();
    Init_CLOCKS();

    /*LED_GPIO-P1.0*/
    P1DIR |=(BIT0);                           //P1.0 mode output
    P1OUT &=~(BIT0);                          //P1.0 output low

    Init_UART();
    delay_ms(1000);                 //延时时间需要较长
    /*test*/

//    /*UART_GPIO*/
    P1SEL1 &= ~(BIT4 | BIT5);                 // USCI_A0 UART operation
    P1SEL0 |= BIT4 | BIT5;                    //UART_PIN
    /*IIC_GPIO*/
    P1SEL1 &= ~(BIT2 | BIT3);                 // USCI_A0 UART operation
    P1SEL0 |= BIT2 | BIT3;

    SYSCFG0 = FRWPPW | DFWP;

    if(Write_flag.mode == cmd03nack)
        Write_flag.count.CMD03 ++;
    if(Write_flag.count.CMD03 == 2)
        Write_flag.mode = normal;
    SYSCFG0 = FRWPPW | PFWP | DFWP;
    /* 芯片上电首先运行到此，初始化硬件IIC */
    if(Write_flag.mode != cmd03nack)
        Init_IIC(printer_ID);
    CLK_7100_SET_OUT;
    CLK_7100_OUT_1;
    /*
    CLK_7100_OUT_1;
    CLK_7100_OUT_0;
    */
    while (1)
    {

        if(flag[0] != 0x37313030)
        {

            /* TEST_START:确定430与7100上电后成功通讯 */

//            while (test_flag!=0x00)
//            {
//                test_flag = f_430_to_7100();
//                delay_ms(500);
//            }


            SYSCFG0 = FRWPPW | DFWP;
//           loop:    f_7100_DATA();
//
//            if(strncmp(FRAM_write,RD_NG,8)!=0)
//            {
//                flag[0] = 0x37313030;
//                for(i=0;i<10;i++)
//               {
//                 delay_ms(250);
//                 P1OUT |= (BIT0);                         //P1.0 output low
//                 delay_ms(250);
//                 P1OUT &=~(BIT0);                         //P1.0 output low
//               }
//            }
//            else {
//             for(i=0;i<5;i++)
//            {
//              delay_ms(250);
//              P1OUT |= (BIT0);                         //P1.0 output low
//              delay_ms(250);
//              P1OUT &=~(BIT0);                         //P1.0 output low
//            }
//                goto loop;
//
//          }
            /*do_while*/
            f_7100_DATA();
         do{
              if(strncmp(FRAM_write,RD_NG,8)!=0)
                 {
                   flag[0] = 0x37313030;
                   for(i=0;i<10;i++)
                  {
                      delay_ms(250);
                      P1OUT |= (BIT0);                         //P1.0 output low
                      delay_ms(250);
                      P1OUT &=~(BIT0);                         //P1.0 output low
                  }
                 }
              else     f_7100_DATA();
              for(i=0;i<2;i++)
             {
               delay_ms(250);
               P1OUT |= (BIT0);                         //P1.0 output low
               delay_ms(250);
               P1OUT &=~(BIT0);                         //P1.0 output low
             }
            }while(flag[0] != 0x37313030);

               for(i=0;i<5;i++)
              {
                delay_ms(250);
                P1OUT |= (BIT0);                         //P1.0 output low
                delay_ms(250);
                P1OUT &=~(BIT0);                         //P1.0 output low
              }
           delay_ms(50);

            memset(&Write_flag, 0, sizeof(Write_flag));
             SYSCFG0 = FRWPPW | PFWP | DFWP;

        }
        else
        {
            __bis_SR_register(LPM0_bits | GIE);             // Enter LPM0 w/ interrupts
        }
    }
}

void Init_CLOCKS(void)
{
// Configure one FRAM waitstate as required by the device datasheet for MCLK
// operation beyond 8MHz before configuring the clock system.
    FRCTL0 = FRCTLPW | NWAITS_1;                       //Change the NWAITS_1 value to add the right amount of waitstates
    __bis_SR_register(SCG0);                           // disable FLL
    CSCTL3 |= SELREF__REFOCLK;                         // Set REFO as FLL reference source， FLLREFDIV bit :000----/1
    CSCTL0 = 0;                                        // clear DCO and MOD registers
    CSCTL1 &= ~(DCORSEL_7);    //fff1                  // Clear DCO frequency select bits first
    CSCTL1 |= DCORSEL_5;                               // Set DCO = 16MHz
    CSCTL2 = FLLD_0 + 487;                             // DCOCLKDIV = 16MHz   ，000b = fDCOCLK ÷ 1，487=0X01E7=0000 0001 1110 0111
                                                       // fDCOCLKDIV =(FLLN+1)*(fFLLREFCLK/n)
                                                       //            =(487+1)*(32.768kHZ/1)=16Mhz

    __delay_cycles(3);
    __bic_SR_register(SCG0);                          // enable FLL
// Disable waiting FLL lock, as it takes about 300ms in active mode.
// Just go to sleep and work with unlocked clock during first operations.
// while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));         // FLL locked
    /*select MCLK,SMCLK,ACLK source*/
    CSCTL4 = SELMS__DCOCLKDIV|SELA__REFOCLK;          // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                                      // default DCOCLKDIV as MCLK and SMCLK source
}
//
void Init_MCU(void)
{
    WDTCTL = WDTPW | WDTHOLD;               // Stop WDT
    // Disable the GPIO power-on default high-impedance mode
    // to activate previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;
}
//
//------------------------------------------------------------------------------
// eUSCI_B0 interrupt service routine for I2C slave communication.
//------------------------------------------------------------------------------
#pragma vector = USCI_B0_VECTOR       //定位到中断向量表上某中断
__interrupt void USCI_B0_ISR(void)
{
//      P1OUT |=(BIT0);                          //P1.0 output low
//      P1OUT &=~(BIT0);                         //P1.0 output low
//      P1OUT |=(BIT0);                          //P1.0 output low
//      P1OUT &=~(BIT0);                         //P1.0 output low
//      P1OUT |=(BIT0);                          //P1.0 output low
//      P1OUT &=~(BIT0);                         //P1.0 output low
  switch(__even_in_range(UCB0IV, USCI_I2C_UCBIT9IFG))
  {
    case USCI_I2C_UCSTTIFG:                   // Vector 6: STTIFG  START_FLAG
        I2Ccount_RX = 0;                      // Reset counters with sequence start
        I2Ccount_TX = 0;
        UCB0IFG &= ~UCSTTIFG;                 // Clear start interrupt flag bit
        /*
        if(Write_flag.mode == cmd03nack)
        {
            if(Write_flag.count.CMD03 == 0)
            {
                UCB0CTLW0 = UCSWRST;
                UCB0CTLW0 |= UCMODE_3 | UCSYNC | UCSSEL__SMCLK;
                UCB0CTLW0 &= ~(UCA10 | UCSLA10);
                UCB0I2COA0 = 0x78 | UCOAEN;
                UCB0CTLW0 &= ~UCSWRST;
            }
            SYSCFG0 = FRWPPW | DFWP;
            if(Write_flag.count.CMD03 <= 2)
            {
                UCB0CTLW0 |= UCTXNACK;
                Write_flag.count.CMD03 ++;
            }
            else
            {
                Write_flag.count.CMD03 = 0;
                Init_IIC(printer_ID);
                Write_flag.mode = normal;
                UCB0CTLW0 &= ~UCTXNACK;
            }
            SYSCFG0 = FRWPPW | PFWP | DFWP;
        }
        */
        if(Write_flag.mode == ID_Restore)
        {
            SYSCFG0 = FRWPPW | DFWP;
            if(Write_flag.count.CMDIDRestore < 2)
            {
                UCB0CTLW0 |= UCTXNACK;          //
                Write_flag.count.CMDIDRestore ++;
            }
            else
            {
                Write_flag.count.CMDIDRestore = 0;
                Write_flag.mode = normal;
                UCB0CTLW0 &= ~UCTXNACK;        //clear NACK
            }
            SYSCFG0 = FRWPPW | PFWP | DFWP;
        }
        break;
    case USCI_I2C_UCSTPIFG:             //STOP interrupt
        UCB0IFG &= ~UCSTPIFG;           //clear interrupt
        cmd_process();
        if(Write_flag.mode == cmd03nack)
        {
            UCB0CTLW0 = UCSWRST;
            UCB0CTLW0 |= UCMODE_3 | UCSYNC | UCSSEL__SMCLK;
            UCB0CTLW0 &= ~(UCA10 | UCSLA10);
            UCB0I2COA0 = 0xff | UCOAEN;
            UCB0CTLW0 &= ~UCSWRST;
        }
        break;
    case USCI_I2C_UCRXIFG1:                 // RX  inturrpt
        I2CRXData[I2Ccount_RX++] = UCB0RXBUF;
        break;
    case USCI_I2C_UCTXIFG1:                 // TX inturrpt
        UCB0TXBUF = returndata[I2Ccount_TX++];
        if((I2CRXData[0] == 0x07)&&(Write_flag.mode == ID_change)&&(I2Ccount_TX == 6))
        {
            SYSCFG0 = FRWPPW | DFWP;
            Init_IIC(printer_ID);
            Write_flag.mode = ID_Restore;
            Write_flag.count.CMDIDRestore = 0;
            SYSCFG0 = FRWPPW | PFWP | DFWP;
        }
        break;
    case USCI_I2C_UCRXIFG0:                   // Vector 24: RXIFG0
        I2CRXData[I2Ccount_RX++] = UCB0RXBUF; // Store received I2C data
        if(I2CRXData[0] == 0x02)
        {
            SYSCFG0 = FRWPPW | DFWP;
            if((Write_flag.mode == data_addnack)&&(I2Ccount_RX == 50))
            {
                UCB0CTLW0 |= UCTXNACK;
                Write_flag.mode = normal;
            }
            if((Write_flag.mode == address_addnack)&&(I2Ccount_RX == 52))
            {
                UCB0CTLW0 |= UCTXNACK;
                Write_flag.mode = special_write;
            }
            SYSCFG0 = FRWPPW | PFWP | DFWP;
        }
        break;
    case USCI_I2C_UCTXIFG0:                   // Vector 26: TXIFG0
        if((I2Ccount_TX == 0)&&(I2CRXData[0] == 0x01))
            address = (uint16_t)(I2CRXData[2]<<8)|(uint16_t)I2CRXData[1];
        send_data();
        break;
    default: break;
  }
}

/**
 *
 * 函数名: Init_UART
 * 参数 :  无
 * 返回值: 无
 * 备注 : ACLK-9600 SMCLK-115200 SMCLK-9600
 *
 * */
void Init_UART(void)
{
       //Configure UART
       UCA0CTLW0 |= UCSWRST;                     // Put eUSCI in reset enable
       UCA0CTLW0 |= UCSSEL__SMCLK;               // clock source select  16Mhz
       //Baud Rate calculation
       /*N = fBRCLK/Baud Rate*/
       UCA0BR0 = 138;                              // 16000000/115200 =138.88888
       UCA0MCTLW = 0xF700;                       // 16000000/115200 - INT(16000000/115200)=0.68 可通过查表22.3.10得到小数部分的值
                                                 // UCBRSx value = 0xF7 (See UG) N=UCA0BR0+UCBRSx
       UCA0BR1 = 0;
       UCA0CTLW0 &= ~UCSWRST;                    // Initialize eUSCI
       UCA0IE |= UCRXIE|UCTXIE;                         // Enable USCI_A0 RX TX interrupt

}
/**
 *
 * 中断
 *
 **/
#pragma vector = USCI_A0_VECTOR      
__interrupt void USCI_A0_ISR(void)
{
 //   switch(__even_in_range(UCA0IV, USCI_I2C_UCBIT9IFG))
    switch(__even_in_range(UCA0IV, USCI_UART_UCTXCPTIFG))
    {
        case USCI_NONE: break;

        case USCI_UART_UCRXIFG:

          rxbuff[ rxcount ] = UCA0RXBUF;
          rxcount ++ ;
          if((  rxcount == 3 ) || (UCA0RXBUF == 0x0D ) )
          {
            rxflag = 1;
          }
              break;

        case USCI_UART_UCTXIFG:
            break;

        case USCI_UART_UCSTTIFG: break;

        case USCI_UART_UCTXCPTIFG: break;
      }
}

int fputc(int ch,FILE *f)
{
    UCA0TXBUF = ch&0xff;
    while(!(UCA0IFG & UCTXIFG));
    return ch;
}
int fputs(const char *_ptr, register FILE *_fp)
{
  unsigned int i, len;

  len = strlen(_ptr);

  for(i=0 ; i<len ; i++){
    UCA0TXBUF = _ptr[i]&0xff;
    while(!(UCA0IFG & UCTXIFG));
  }

  return len;
}

void Send_Char(uint8_t dat)
{
    while(!(UCA0IFG & UCTXIFG));
    UCA0TXBUF = dat&0xff;
}
void Send_string(uint8_t *ptr)
{
    while(*ptr!='\0')
    {
        Send_Char(*ptr++);
    }
    Send_Char('\n');
}

在FRAM与RAM中的数据比较有什么特殊的地方么？

最主要的一个区别是：

（MSP430 FRAM 技术–操作方法和最佳实践 (Rev. B)）

（MSP430FR2433 混合信号微控制器 datasheet (Rev. F) 5.3 Recommended Operating Conditions）

有关Wait State Control的内容，请参考MSP430FR4xx and MSP430FR2xx family user's guide (Rev. I) 6.5 Wait State Control

你好，如果在实际使用MSP430FR2433 BSL 的IIC烧录程序。对于txt码表应该如何处理

@c400
1C
@cc1c
01 FD 00 00 0F 51 03 00 00 83 00 00 FD 01 00 21
01 01 00 02 01 00 FF 03 01 00 04 01 00 05 01 FF
00 06 01 00 07 82 01 01 FF 80 01 10 03 01 01 83
01 BB 01 FF 00 04 FC 05 FC 00 B0 81 03 00 01 FF
F0 00 D0 D5 00 00 A8 D1 00 00 0E D6 00 00 00 00
1D 00 00 00 1C CC 00 00 00 20 00 00 6A CC 00 00
A0 20 00 00 B2 40 02 A5 60 01 5F 42 00 20 2F 83
48 24 3F 80 03 00 22 24 3F 80 1B 00 B3 24 3F 80
61 00 BD 20 B2 90 03 00 B4 20 0C 34 A2 42 12 CC
D2 42 01 20 9D 20 3F 40 40 00 5F 52 01 20 C2 4F
0D CC AD 3C 5F 42 0D CC 3F 50 10 00 82 4F 4E 05
B0 13 92 CF F2 50 40 00 0D CC A1 3C 0F 43 2F 92
1D 34 0F 43 2F 92 06 34 DF 4F 01 20 0E CC 1F 53
2F 92 FA 3B F2 F0 3F 00 0F CC F2 90 40 00 11 CC
03 2C F2 50 40 00 11 CC F2 90 C0 00 11 CC 03 28
F2 80 40 00 11 CC 1F 53 2F 92 E3 3B C2 43 09 CC
7E 3C 5F 42 02 20 47 18 0F 5F 5E 42 01 20 0E DF
82 4E 02 CC 5F 42 B4 20 7F 80 03 00 C2 4F 06 CC
92 92 04 CC 02 CC 12 20 5E 42 07 CC 5F 42 06 CC
0F 8E 2F 92 0B 20 D2 53 0B CC F2 90 0B 00 0B CC
05 20 C2 43 0B CC B2 40 05 00 12 CC 1F 42 02 CC
1F 82 04 CC 3F 90 10 00 0F 20 D2 92 07 CC 06 CC
0B 20 D2 53 0C CC F2 90 03 00 0C CC 05 20 C2 43
0C CC B2 40 06 00 12 CC 92 42 02 CC BA 20 5F 42
06 CC 82 4F B8 20 B2 90 07 00 12 CC 03 20 B2 F0
FC FF B8 20 0F 43 1F 92 B8 20 0A 2C CE 0F 1E 52
BA 20 DE 4F 03 20 02 C4 1F 53 1F 92 B8 20 F6 2B
92 42 02 CC 04 CC D2 42 06 CC 07 CC B2 90 07 00
12 CC 1D 20 92 43 40 05 B2 D0 88 07 40 05 B2 F0
FF 3F 40 05 B2 40 01 04 54 05 92 C3 40 05 82 43
12 CC 0D 3C 5C 42 00 C4 B0 13 B2 D6 A2 43 12 CC
0D 14 3D 40 67 0A 1D 83 FE 23 0D 16 03 43 D2 42
00 20 BC 20 B2 40 03 A5 60 01 10 01 4F 14 1F 42
6E 05 3F 80 06 00 84 24 2F 83 6D 24 3F 80 0A 00
9E 24 2F 83 43 24 2F 83 14 24 2F 83 A2 20 82 93
B6 20 0C 20 D2 93 00 20 09 20 5F 42 02 20 47 18
0F 5F 5E 42 01 20 0E DF 82 4E BA 20 B0 13 B8 D0
90 3C 1E 42 B4 20 CF 0E 1F 53 82 4F B4 20 1F 42
4C 05 CE 4F 00 20 E2 93 00 20 83 20 B2 40 02 A5
60 01 B2 90 05 00 12 CC 08 20 B2 90 32 00 B4 20
04 20 B2 D2 40 05 82 43 12 CC B2 90 06 00 12 CC
09 20 B2 90 34 00 B4 20 05 20 B2 D2 40 05 B2 40
07 00 12 CC B2 40 03 A5 60 01 63 3C 1E 42 B6 20
CF 0E 1F 53 82 4F B6 20 5F 4E 96 20 82 4F 4E 05
F2 90 07 00 00 20 55 20 A2 93 12 CC 52 20 B2 90
06 00 B6 20 4E 20 B2 40 02 A5 60 01 5C 42 9E 20
B0 13 B2 D6 B2 40 03 00 12 CC C2 43 08 CC B2 40
03 A5 60 01 3E 3C B2 C2 6C 05 B0 13 80 CC 92 93
12 CC 37 20 92 43 40 05 B2 D0 80 07 40 05 B2 F0
FF 3F 40 05 B2 40 FF 04 54 05 92 C3 40 05 29 3C
82 43 B4 20 82 43 B6 20 A2 C2 6C 05 B2 90 03 00
12 CC 1F 20 B2 40 02 A5 60 01 E2 93 08 CC 07 28
C2 43 08 CC 82 43 12 CC B2 C2 40 05 04 3C B2 D2
40 05 D2 53 08 CC B2 40 03 A5 60 01 0A 3C 1E 42
B4 20 CF 0E 1F 53 82 4F B4 20 1F 42 4C 05 CE 4F
00 20 4B 16 00 13 21 82 CC 01 0D 43 3E 40 03 00
B0 13 D2 D7 3C 40 88 20 3D 40 B1 20 5E 42 89 20
5F 42 8A 20 B0 13 96 D2 0D 14 3D 40 67 0A 1D 83
FE 23 0D 16 03 43 3C 40 8B 20 3D 40 B1 20 5E 42
8C 20 5F 42 8D 20 B0 13 96 D2 0D 14 3D 40 67 0A
1D 83 FE 23 0D 16 03 43 5E 42 83 20 5F 42 84 20
3C 40 82 20 3D 40 B0 20 B0 13 96 D2 0D 14 3D 40
67 0A 1D 83 FE 23 0D 16 03 43 3C 40 9C 20 3D 40
B0 20 6E 43 0F 43 B0 13 96 D2 0D 14 3D 40 67 0A
1D 83 FE 23 0D 16 03 43 5E 42 83 20 5F 42 84 20
3C 40 82 20 CD 01 B0 13 96 D2 0D 14 3D 40 67 0A
1D 83 FE 23 0D 16 03 43 3C 40 00 20 3D 40 B0 20
7E 40 0F 00 0F 43 B0 13 96 D2 0D 14 3D 40 67 0A
1D 83 FE 23 0D 16 03 43 11 3C CD 01 1D 53 5E 42
83 20 5F 42 84 20 3C 40 82 20 B0 13 96 D2 0D 14
3D 40 67 0A 1D 83 FE 23 0D 16 03 43 5E 42 9D 20
5F 41 01 00 0F 8E 3F 90 80 00 E7 3B 3C 40 85 20
5E 42 86 20 5F 42 87 20 3D 40 A0 20 B0 13 96 D2
3C 40 0A 00 B0 13 B8 D7 21 52 10 01 B2 40 02 A5
60 01 5F 42 00 20 1F 83 63 24 2F 83 37 24 3F 80
03 00 16 24 1F 83 57 24 3F 80 79 00 47 24 2F 83
03 24 1F 83 3F 24 5E 3C A2 92 12 CC 04 24 B2 40
38 00 4E 05 57 3C 5F 42 0D CC 82 4F 4E 05 52 3C
F2 90 10 00 09 CC 0B 28 B2 90 03 00 B6 20 04 38
B2 40 40 00 4E 05 09 3C 82 43 4E 05 06 3C 1F 42
B6 20 5F 4F 0E CC 82 4F 4E 05 B2 90 03 00 B6 20
02 20 D2 53 09 CC 92 53 B6 20 34 3C D2 92 00 20
BC 20 03 24 C2 43 0A CC 02 3C D2 53 0A CC F2 90
03 00 0A CC 04 20 C2 43 0A CC 92 43 12 CC 82 43
4E 05 20 3C B2 40 F0 00 4E 05 1C 3C 1E 42 B6 20
CF 0E 1F 53 82 4F B6 20 5F 4E A0 20 82 4F 4E 05
82 43 12 CC 0F 3C 5C 42 9E 20 B0 13 B2 D6 0A 3C
1F 42 BA 20 1F 52 B6 20 5F 4F 02 C4 82 4F 4E 05
92 53 B6 20 B2 40 03 A5 60 01 10 01 6A 14 B0 13
84 D2 67 4B 47 47 06 43 2D 3C C9 0E CA 0F 09 88
0A 73 19 83 0A 73 C5 09 C8 0A 19 53 0A 63 0F 18
48 58 00 18 48 D5 65 48 C4 0E C8 0F 1E 53 0F 63
0F 18 48 58 00 18 48 D4 C8 45 00 00 1B 83 EB 23
0D 3C B0 13 84 D2 6A 4B C9 0E CB 0F 1E 53 0F 63
0F 18 4B 5B 00 18 4B D9 CB 4A 00 00 57 03 16 53
36 92 CD 37 17 B3 ED 23 B0 13 84 D2 68 4B 48 48
B0 13 84 D2 6B 4B 4B 4B CA 08 5A 0E C8 0B 58 0F
38 F0 0F 00 08 DA 3B F0 0F 00 3B 50 03 00 3B 90
12 00 1D 20 C9 0C CA 0D 1C 53 0D 63 0F 18 4A 5A
00 18 4A D9 6A 4A 4A 4A 3A B0 80 00 0F 24 C5 0C
C9 0D 1C 53 0D 63 0F 18 49 59 00 18 49 D5 69 49
3A F0 7F 00 49 49 46 18 09 59 0A D9 0B 5A 38 90
FF 0F 9B 23 64 16 10 01 CA 0C CB 0D 1C 53 0D 63
0F 18 4B 5B 00 18 4B DA 10 01 3A 14 CB 0F CA 0E
C7 0C 59 43 B0 13 7E D6 7C 40 F0 00 B0 13 D6 D3
5C 43 B0 13 D6 D3 4C 93 02 24 4C 43 3D 3C 08 43
4F 4A 08 9F 0D 2C CF 07 0F 58 6C 4F B0 13 D6 D3
4C 93 05 20 18 53 4F 4A 08 9F F5 2B 01 3C 49 43
0D 14 3D 40 07 00 1D 83 FE 23 0D 16 03 43 0B 93
20 24 B0 13 7E D6 7C 40 F1 00 B0 13 D6 D3 4C 93
02 24 4C 43 19 3C 08 43 09 3C B0 13 46 D5 CF 0D
0F 58 CF 4C 00 00 B0 13 46 D7 18 53 CF 0B 1F 83
08 9F F3 2B B0 13 46 D5 0D 5B CD 4C FF FF B0 13
E4 D6 B0 13 16 D7 CC 09 37 16 10 01 B0 13 E6 D7
B0 13 4A D6 F2 D0 0C 00 0A 02 B2 40 02 A5 60 01
92 93 12 CC 02 20 D2 53 0A CC E2 93 0A CC 02 20
82 43 12 CC B2 40 03 A5 60 01 92 93 12 CC 04 24
5C 42 9E 20 B0 13 B2 D6 E2 D2 24 02 E2 D2 22 02
1E 3C B2 40 02 A5 60 01 B0 13 62 D4 3C 40 02 C4
3D 40 8E 20 3E 42 B0 13 72 D7 0C 93 06 24 B2 40
30 30 14 CC B2 40 31 37 16 CC 3C 40 02 CC 0D 43
3E 40 12 00 B0 13 D2 D7 B2 40 03 A5 60 01 B2 90
31 37 16 CC DE 23 B2 90 30 30 14 CC DA 23 03 43
32 D0 18 00 03 43 F3 3F 03 43 5F 43 F2 D0 80 00
05 02 4E 43 7E 90 09 00 3C 2C 7E 92 1C 24 E2 C2
22 02 7C B0 80 FF 04 20 F2 F0 7F 00 03 02 03 3C
F2 D0 80 00 03 02 4C 5C 0D 14 2D 43 1D 83 FE 23
0D 16 03 43 E2 D2 22 02 0D 14 2D 43 1D 83 FE 23
0D 16 03 43 1A 3C E2 C2 22 02 0D 14 2D 43 1D 83
FE 23 0D 16 03 43 F2 F0 7F 00 05 02 E2 D2 22 02
F2 B0 80 FF 01 02 01 20 4F 43 0D 14 2D 43 1D 83
FE 23 0D 16 03 43 E2 C2 22 02 5E 53 7E 90 09 00
C4 2B CC 0F 10 01 0A 14 0A 43 3A 92 37 34 3C 40
64 20 3D 40 B0 20 5E 43 1F 43 B0 13 96 D2 0D 14
3D 40 67 0A 1D 83 FE 23 0D 16 03 43 3C 40 67 20
3D 40 B0 20 5E 43 1F 43 B0 13 96 D2 0D 14 3D 40
67 0A 1D 83 FE 23 0D 16 03 43 CC 0A 5C 02 0C 5A
3C 50 6A 20 4D 4A 8D 10 3D 50 02 C4 7E 40 03 00
3F 40 00 01 B0 13 96 D2 0D 14 3D 40 67 0A 1D 83
FE 23 0D 16 03 43 1A 53 3A 92 C9 3B 0A 16 10 01
2A 14 19 42 CC 01 B2 40 80 5A CC 01 3F 40 5E CC
9F 00 6A CC 21 24 3F 40 70 CC 9F 00 80 CC 1C 24
3A 40 80 CC 3A 80 70 CC 5A 09 38 40 70 CC 3C 48
3D 48 CE 0C CF 0D 1C 53 0D 63 0F 18 4F 5F 00 18
4F DE 6F 4F 4F 4F 5F 06 00 18 5B 4F 5E CC 3E 48
3F 48 4B 13 1A 83 EB 23 79 C2 39 D0 08 5A 82 49
CC 01 B0 13 04 D8 28 16 10 01 4C 43 F2 F0 7F 00
05 02 4F 43 7F 92 1B 2C 4C 5C E2 C2 22 02 0D 14
2D 43 1D 83 FE 23 0D 16 03 43 E2 D2 22 02 F2 B0
80 FF 01 02 02 20 5C C3 01 3C 5C D3 0D 14 2D 43
1D 83 FE 23 0D 16 03 43 5F 53 7F 92 E5 2B E2 C2
22 02 10 01 0A 14 1A 41 08 00 1B 41 0A 00 0F 18
4D 5D 00 18 4D DC 0F 18 4F 5F 00 18 4F DE 0B 93
02 20 0A 93 0D 24 0C 43 0E 43 AD 00 01 00 FD 4F
FF FF 1C 53 0E 63 0E 9B F8 2B 02 20 0C 9A F5 2B
0A 16 10 01 0A 14 1C 53 0D 63 0F 18 4D 5D 00 18
4D DC 2C 4D 1B 4D 02 00 0B 93 02 20 0C 93 0F 24
CA 0E CD 0F 1E 53 0F 63 0F 18 4D 5D 00 18 4D DA
CD 43 00 00 1C 83 0B 73 F3 23 0C 93 F1 23 0A 16
10 01 0A 14 21 82 CB 0C CA 0D CC 0E CD 0F CE 0B
CF 0A CA 0E CB 0F 1A 53 0B 63 0F 18 4B 5B 00 18
4B DA 1A 4B 02 00 A1 4B 00 00 81 4A 02 00 3E 50
05 00 0F 63 B0 13 90 D5 21 52 0A 16 10 01 B2 40
10 A5 A0 01 32 D0 40 00 B2 D0 10 00 86 01 82 43
80 01 B2 F0 F1 FF 82 01 B2 D0 0A 00 82 01 B2 40
E7 01 84 01 00 3C 03 43 32 C0 40 00 82 43 88 01
10 01 F2 D0 80 00 05 02 F2 D0 80 00 03 02 E2 D2
22 02 0D 14 2D 43 1D 83 FE 23 0D 16 03 43 F2 F0
7F 00 03 02 0D 14 2D 43 1D 83 FE 23 0D 16 03 43
E2 C2 22 02 10 01 92 43 40 05 B2 D0 00 07 40 05
B2 D0 00 C0 40 05 B2 D0 80 00 40 05 4C 4C 3C D0
00 84 82 4C 54 05 B2 40 00 04 56 05 92 C3 40 05
B2 D0 0F 03 6A 05 10 01 E2 C2 22 02 F2 D0 80 00
05 02 F2 F0 7F 00 03 02 F2 D0 80 00 03 02 E2 D2
22 02 0D 14 2D 43 1D 83 FE 23 0D 16 03 43 E2 C2
22 02 F2 F0 7F 00 03 02 10 01 F2 D0 80 00 05 02
F2 F0 7F 00 03 02 E2 D2 22 02 0D 14 2D 43 1D 83
FE 23 0D 16 03 43 F2 D0 80 00 03 02 0D 14 2D 43
1D 83 FE 23 0D 16 03 43 10 01 E2 C2 22 02 F2 D0
80 00 05 02 F2 F0 7F 00 03 02 E2 D2 22 02 0D 14
2D 43 1D 83 FE 23 0D 16 03 43 E2 C2 22 02 F2 F0
7F 00 03 02 10 01 0A 14 0E 93 0F 24 CF 0C 6B 4D
6C 4F 4A 4C 0A 9B 03 24 4C 4C 0C 8B 07 3C 0B 93
04 24 1F 53 1D 53 1E 83 F2 23 0C 43 0A 16 10 01
31 40 00 30 B0 13 00 D8 0C 93 02 24 B0 13 DC D4
0C 43 B0 13 38 D3 1C 43 B0 13 FA D7 0F 43 0F 9C
09 2C 0D 14 3D 40 D2 14 1D 83 FE 23 0D 16 1F 53
0F 9C F7 2B 10 01 CF 0C 0E 93 06 24 4D 4D 1F 53
CF 4D FF FF 1E 83 FB 23 10 01 B2 40 80 5A CC 01
92 C3 30 01 10 01 32 D0 10 00 FD 3F 03 43 03 43
FF 3F 03 43 1C 43 10 01 10 01
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FF FF FF FF FF FF FF FF
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F2 D7 F2 D7 F2 D7 28 CE F2 D7 F2 D7 F2 D7 F2 D7
F2 D7 F2 D7 F2 D7 F2 D7 F2 D7 F2 D7 F2 D7 F2 D7
F2 D7 F2 D7 9C D7
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