J722SXH01EVM: Is there a function in c7000 dsplib equal to DSPF_sp_biquad in C6000 dsplib

Hi,

Could you please refer this : https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1619770/faq-tda4vh-q1-dsplib-mathlib-steps-to-migrate-c66x-source-code-to-c7x 

I will go through the remaining questions from my end and respond to you shortly.

I did not find someting to do with the  dsplib biquadfunction

I did not find someting to do with the biquad function in dsplib

As mentioned earlier, we cannot directly use the cascade biquad code from DSPLIB for sp_biquad. It will behave the same as sp_biquad only if the required modifications are applied.

1) numStages = 1, DSPF_sp_biquad processes one biquad stage per call.

2) Coeff layout :
   DSPF_sp_biquad --> 
   b = {b0,b1,b2}
   a = {1,a1,a2}
   DSPLIB_cascadeBiquad_exec --->
   coeff = {b0,b1,b2,a2,a1}
3) Align Filter state representation :
   DSPF_sp_biquad -->
   delay [0] , delay[1]
   DSPLIB_cascadeBiquad_exec --->
   vd0, vd1 per stage.
4) Simplify the multistage pipeline ->
   Kept only stage1 logic and removed remaining stages.
5) Remove output gain scaling as we only use single stage.
   ie, output = y
6) Input/Output Buffer Access -
   numChannels = 1
   dataBufferInPitch = 1
   dataBufferOutPitch = 1

Please refer to the test code attached below for these changes.

void DSPF_sp_biquad(float *x, float *b, float *a,
    float *delay, float *y, const int nx)
{
    int i;

    for (i = 0; i < nx; i++)
    {
        y[i] = b[0] * x[i] + delay[0];
        delay[0] = b[1] * x[i] - a[1] * y[i] + delay[1];
        delay[1] = b[2] * x[i] - a[2] * y[i]; 
    }
}

/* ====================================================================================================
                                         C7x Cascade Biquad
======================================================================================================= */
typedef void* DSPLIB_kernelHandle;

typedef struct {
    uint32_t dataSize;
    uint32_t numStages;
    uint32_t numChannels;
} DSPLIB_cascadeBiquad_InitArgs;

typedef struct {
    DSPLIB_cascadeBiquad_InitArgs initArgs;
    uint32_t dataBufferInPitch;
    uint32_t dataBufferOutPitch;
    uint32_t filterVarPitch;
} DSPLIB_cascadeBiquad_PrivArgs;

template <typename dataType>
void DSPLIB_cascadeBiquad_exec(
        DSPLIB_kernelHandle handle,
        void *pIn,
        void *pFilterCoeff,
        void *pFilterVar,
        void *pOut)
{
    DSPLIB_cascadeBiquad_PrivArgs *args =
        (DSPLIB_cascadeBiquad_PrivArgs*)handle;

    dataType *input = (dataType*)pIn;
    dataType *coeff = (dataType*)pFilterCoeff;
    dataType *state = (dataType*)pFilterVar;
    dataType *output = (dataType*)pOut;

    int N = args->initArgs.dataSize;

    dataType b0 = coeff[0];
    dataType b1 = coeff[1];
    dataType b2 = coeff[2];
    dataType a1 = coeff[3];
    dataType a2 = coeff[4];

    dataType d0 = state[0];
    dataType d1 = state[1];

    for(int i=0;i<N;i++)
    {
        dataType x = input[i];

        dataType y = b0*x + d0;

        d0 = b1*x - a1*y + d1;
        d1 = b2*x - a2*y;

        output[i] = y;
    }

    state[0] = d0;
    state[1] = d1;
}

If you intend to port the C66x sp_biquad implementation to C7x, you can follow the steps provided in the FAQ [ https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1619770/faq-tda4vh-q1-dsplib-mathlib-steps-to-migrate-c66x-source-code-to-c7x]. The FAQ also includes training material that explains how to configure the streaming engine parameters.