DSP6655的DDR3初始化步骤

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#include "KeyStone_common.h"
#include "tistdtypes.h"

// Chip Level Register
#define CHIP_LEVEL_REG  0x02620000
#define DEVSTAT                     (*(unsigned int*)(CHIP_LEVEL_REG + 0x0020))
#define KICK0                       (*(unsigned int*)(CHIP_LEVEL_REG + 0x0038))
#define KICK1                       (*(unsigned int*)(CHIP_LEVEL_REG + 0x003C))
#define TINPSEL                     (*(unsigned int*)(CHIP_LEVEL_REG + 0x0300))
#define TOUTPSEL                    (*(unsigned int*)(CHIP_LEVEL_REG + 0x0304))
#define MAINPLLCTL0                 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0328))
#define MAINPLLCTL1                 (*(unsigned int*)(CHIP_LEVEL_REG + 0x032C))
#define DDR3PLLCTL0                 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0330))
#define DDR3PLLCTL1                 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0334))
#define OBSCLKCTL                   (*(unsigned int*)(CHIP_LEVEL_REG + 0x03AC)) //TODO:find out obsc, it may not require. as it useful for PA
#define PIN_CONTROL_0               (*(unsigned int*)(CHIP_LEVEL_REG + 0x0580))
#define PIN_CONTROL_1               (*(unsigned int*)(CHIP_LEVEL_REG + 0x0584))

// DDR3 Configuration Register,DDR3_CONFIG_[2:10]
#define DATA0_WRLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x040C))
#define DATA1_WRLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x0410))
#define DATA2_WRLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x0414))
#define DATA3_WRLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x0418))
#define DATA4_WRLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x041C))
#define DATA5_WRLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x0420))
#define DATA6_WRLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x0424))
#define DATA7_WRLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x0428))
#define DATA8_WRLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x042C))

// DDR3 Configuration Register,DDR3_CONFIG_[14:22]
#define DATA0_GTLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x043C))
#define DATA1_GTLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x0440))
#define DATA2_GTLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x0444))
#define DATA3_GTLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x0448))
#define DATA4_GTLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x044C))
#define DATA5_GTLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x0450))
#define DATA6_GTLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x0454))
#define DATA7_GTLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x0458))
#define DATA8_GTLVL_INIT_RATIO      (*(unsigned int*)(CHIP_LEVEL_REG + 0x045C))

// DDR3 Configuration Register,DDR3_CONFIG_[0,12,23,24]
#define DDR3_CONFIG_REG_0           (*(unsigned int*)(CHIP_LEVEL_REG + 0x0404))
#define DDR3_CONFIG_REG_12          (*(unsigned int*)(CHIP_LEVEL_REG + 0x0434))
#define DDR3_CONFIG_REG_23          (*(unsigned int*)(CHIP_LEVEL_REG + 0x0460))
#define DDR3_CONFIG_REG_24          (*(unsigned int*)(CHIP_LEVEL_REG + 0x0464))

#define SGMII_SERDES_STS			(*(unsigned int*)(CHIP_LEVEL_REG + 0x158))
#define SGMII_SERDES_CFGPLL         (*(unsigned int*)(CHIP_LEVEL_REG + 0x340))
#define SGMII_SERDES_CFGRX0         (*(unsigned int*)(CHIP_LEVEL_REG + 0x344))
#define SGMII_SERDES_CFGTX0         (*(unsigned int*)(CHIP_LEVEL_REG + 0x348))

#define KICK0_UNLOCK (0x83E70B13)
#define KICK1_UNLOCK (0x95A4F1E0)
#define KICK_LOCK    0

// DDR3 Memory Controller Registers definitions
#define DDR_BASE_ADDR          0x21000000

#define DDR_MIDR                    (*(unsigned int*)(DDR_BASE_ADDR + 0x00000000))
#define DDR_SDCFG                   (*(unsigned int*)(DDR_BASE_ADDR + 0x00000008))
#define DDR_SDRFC                   (*(unsigned int*)(DDR_BASE_ADDR + 0x00000010))
#define DDR_SDTIM1                  (*(unsigned int*)(DDR_BASE_ADDR + 0x00000018))
#define DDR_SDTIM2                  (*(unsigned int*)(DDR_BASE_ADDR + 0x00000020))
#define DDR_SDTIM3                  (*(unsigned int*)(DDR_BASE_ADDR + 0x00000028))
#define DDR_PMCTL                   (*(unsigned int*)(DDR_BASE_ADDR + 0x00000038))
#define DDR_ZQCFG                   (*(unsigned int*)(DDR_BASE_ADDR + 0x000000C8))
#define DDR_RDWR_LVL_RMP_CTRL       (*(unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
#define DDR_TMPALRT                 (*(unsigned int*)(DDR_BASE_ADDR + 0x000000CC))
#define DDR_RDWR_LVL_CTRL           (*(unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
#define DDR_DDRPHYC                 (*(unsigned int*)(DDR_BASE_ADDR + 0x000000E4))



/****************************************************************************
 *
 * NAME
 *      Init_Pll2 (unsigned int multiplier, unsigned int divider)
 *
 * PURPOSE:
 *      Setup PLL 2 frequency for DDR3 clock.
 *      The Frequency is based on an external ddr3 clk input ref of 66.65 MHz clock.
 *
 * USAGE
 *      This routine can be called as:
 *
 *      Init_Pll2( unsigned int multiplier, unsigned int divider)
 *
 *      multiplier - (i) Multiplier
 *      divider    - (i) Divider
 *      Note that the values above are actual register values, i.e.,
 *      the computed values - 1
 * RETURN VALUE
 *      None
 *
 * REFERENCE
 *
 ****************************************************************************/
void Init_Pll2(unsigned int multiplier, unsigned int divider)
{
    unsigned int temp, i;

   // GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n");
    puts ( "DDR3 PLL (PLL2) Setup ... \n");

    /*Unlock Boot Config*/
    KICK0 = 0x83E70B13;
    KICK1 = 0x95A4F1E0;

    if (DNUM == 0)
    {
        /* 1. In DDR3PLLCTL1, write ENSAT = 1 (for optimal PLL operation)            *
         * Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control *
         * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1.      *
         * The PLL initialization sequence in the boot ROM sets this bit to 0 and    *
         * could lead to non-optimal PLL operation. Software can set the bit to the  *
         * optimal value of 1 after boot                                             *
         * DDR3PLLCTL1 Bit map                                                         *
         * |31...7   |6     |5 4       |3...0      |                                 *
         * |Reserved |ENSAT |Reserved  |BWADJ[11:8]|                                 */
        DDR3PLLCTL1 |= 0x00000040;

        /* 2. Put the PLL in PLL Mode                                                *
         * DDR3PLLCTL0 Bit map                                                       *
         * |31...24    |23     |22...19       |18...6   |5...0 |                     *
         * |BWADJ[7:0] |BYPASS |Reserved      |PLLM     |PLLD  |                     */
        DDR3PLLCTL0 |= 0x00800000; /* Set the Bit 23 */

        /* 3. Program the necessary multipliers/dividers and BW adjustments          */
        /* part of 3, Set the Multipler values */
        DDR3PLLCTL0 &= ~(0x0007FFC0);
        DDR3PLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
        /* part of 3, Set the divider values */
        DDR3PLLCTL0 &= ~(0x0000003F);
        DDR3PLLCTL0 |= (divider & 0x0000003F);

        /* 4. Set the BWADJ */
        temp = ((multiplier + 1) >> 1) - 1;
        DDR3PLLCTL0 &= ~(0xFF000000);
        DDR3PLLCTL0 |= ((temp << 24) & 0xFF000000);
        DDR3PLLCTL1 &= ~(0x0000000F);
        DDR3PLLCTL1 |= ((temp >> 8) & 0x0000000F);

         /* 5. In PLL Controller, reset the PLL (bit 13 in DDR3PLLCTL1 register)         */
        DDR3PLLCTL1 |= 0x00002000;

        /* 6. Wait for the PLL Reset time (min: 5 us)                                */
        //Delay_milli_seconds(1);
        TSC_delay_ms(1);

        /* 7. In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset */
        DDR3PLLCTL1 &= ~(0x00002000);

        /* 8. Wait at least 500 * REFCLK cycles * PLLD (this is the PLL lock time) */
        //Delay_milli_seconds(1);
        TSC_delay_ms(1);

        /* 9. Put the PLL in PLL Mode                                               *
         * DDR3PLLCTL0 Bit map                                                      *
         * |31...24    |23     |22...19       |18...6   |5...0 |                    *
         * |BWADJ[7:0] |BYPASS |Reserved      |PLLM     |PLLD  |                    */
        DDR3PLLCTL0 &= ~(0x00800000); /* ReSet the Bit 23 */

        //GEL_TextOut( "DDR3 PLL Setup... Done.\n" );
        puts( "DDR3 PLL Setup... Done.\n" );
    }
    else
    {
        //GEL_TextOut("DSP core #%d cannot set DDR3 PLL\n",,2,,,DNUM);
        printf("DSP core #%d cannot set DDR3 PLL\n",DNUM);
    }
}


void ddr3_setup_auto_lvl_1333()
{
    int i,TEMP,startlo, stoplo,starthi, stophi;
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

    /* Wait for PLL to lock = min 500 ref clock cycles.
       With refclk = 100MHz, = 5000 ns = 5us */
  //  Delay_milli_seconds(1); //20161226ע��
    TSC_delay_ms(1);

    /***************** 3.2 DDR3 PLL Configuration ************/
    /* Done before */

    /**************** 3.0 Leveling Register Configuration ********************/
    /* Using partial automatic leveling due to errata */

    /**************** 3.3 Leveling register configuration ********************/
    DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
    DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
    DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
    DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15

    //From 4.2.1 Executing Partial Automatic Leveling -- Start
    DDR3_CONFIG_REG_23 |= 0x00000200;    //Set bit 9 = 1 to use forced ratio leveling for read DQS
    //From 4.2.1 Executing Partial Automatic Leveling -- End

    //Values with invertclkout = 1
    /**************** 3.3 Partial Automatic Leveling ********************/
    // DDR3 Configuration Register,DDR3_CONFIG_[2:10]
    DATA0_WRLVL_INIT_RATIO = 0x00;
    DATA1_WRLVL_INIT_RATIO = 0x00;
    DATA2_WRLVL_INIT_RATIO = 0x00;
    DATA3_WRLVL_INIT_RATIO = 0x00;
    DATA4_WRLVL_INIT_RATIO = 0x33;
    DATA5_WRLVL_INIT_RATIO = 0x3A;
    DATA6_WRLVL_INIT_RATIO = 0x2C;
    DATA7_WRLVL_INIT_RATIO = 0x2C;
    DATA8_WRLVL_INIT_RATIO = 0x21;

    // DDR3 Configuration Register,DDR3_CONFIG_[14:22]
    DATA0_GTLVL_INIT_RATIO = 0x00;
    DATA1_GTLVL_INIT_RATIO = 0x00;
    DATA2_GTLVL_INIT_RATIO = 0x00;
    DATA3_GTLVL_INIT_RATIO = 0x00;
    DATA4_GTLVL_INIT_RATIO = 0xB7;
    DATA5_GTLVL_INIT_RATIO = 0xB1;
    DATA6_GTLVL_INIT_RATIO = 0xA4;
    DATA7_GTLVL_INIT_RATIO = 0xA4;
    DATA8_GTLVL_INIT_RATIO = 0x98;

    //Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
    DDR_DDRPHYC &= ~(0x00008000);
    DDR_DDRPHYC |= (0x00008000);
    DDR_DDRPHYC &= ~(0x00008000);

    /***************** 3.4 Basic Controller and DRAM Configuration ************/
    DDR_SDRFC    = 0x0000515C;    // enable configuration

    /* DDR_SDTIM1   = 0x1557B9BD; */
    TEMP = 0;
    TEMP |= 0x09 << 25; // T_RP bit field 28:25
    TEMP |= 0x09 << 21; // T_RCD bit field 24:21
    TEMP |= 0x09 << 17; // T_WR bit field 20:17
    TEMP |= 0x17 << 12; // T_RAS bit field 16:12
    TEMP |= 0x20 << 6; // T_RC bit field 11:6
    TEMP |= 0x1 << 3; // T_RRD bit field 5:3
    TEMP |= 0x4; // T_WTR bit field 2:0
    DDR_SDTIM1 = TEMP;

    /* DDR_SDTIM2   = 0x304F7FE3; */
    TEMP = 0;
    TEMP |= 0x3 << 28; // T_XP bit field 30:28
    TEMP |= 0x71 << 16; // T_XSNR bit field 24:16
    TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6
    TEMP |= 0x4 << 3; // T_RTP bit field 5:3
    TEMP |= 0x3; // T_CKE bit field 2:0
    DDR_SDTIM2 = TEMP;

    /*  DDR_SDTIM3   = 0x559F849F; */
    TEMP = 0;
    TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)
    TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)
    TEMP |= 0x4 << 21; // T_CKESR bit field 23:21
    TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15
    TEMP |= 0x6A << 4; // T_RFC bit field 12:4
    TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)
    DDR_SDTIM3 = TEMP;

    DDR_DDRPHYC  = 0x0010010F;

    DDR_ZQCFG    = 0x70074c1f;

    DDR_PMCTL    = 0x0;

    //DDR_SDRFC = 0x0000144F; // enable configuration

    /* DDR_SDCFG    = 0x63077AB3; */
    /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32;    // last config write DRAM init occurs */
    TEMP = 0;
    TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)
    TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27
    TEMP |= 0x2 << 24; // DDR_TERM bit field 26:24
    TEMP |= 0x2 << 21; // DYN_ODT bit field 22:21
    TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18
    TEMP |= 0x3 << 16; // CWL bit field 17:16
    TEMP |= 0x1 << 14; // NM bit field 15:14
    TEMP |= 0xE << 10; // CL bit field 13:10
    TEMP |= 0x5 << 7; // ROWSIZE bit field 9:7
    TEMP |= 0x3 << 4; // IBANK bit field 6:4
    TEMP |= 0x0 << 3; // EBANK bit field 3:3
    TEMP |= 0x2; // PAGESIZE bit field 2:0
    DDR_SDCFG = TEMP;

    //Wait 600us for HW init to complete
   // Delay_milli_seconds(1); //20161226ע��
    TSC_delay_ms(1);

    DDR_SDRFC = 0x0000144F;       //Refresh rate = (7.8*666MHz)

    /**************** 4.2.1 Executing Partial Automatic Leveling ********************/

    DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling

    DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value

    //(0x34) instead
    //Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
    //Actual time = ~10-15 ms
   // Delay_milli_seconds(1); //20161226ע��
    TSC_delay_ms(1);

    //GEL_TextOut("\nDDR3 initialization is complete.\n");
    puts("\nDDR3 initialization is complete.\n");

}


/**
 *  @brief Simple DDR3 test
 *
 *  @details
 *      This function performs a simple DDR3 test for a memory range
 *      specified below and returns -1 for failure and 0 for success.
 */

#define DDR3_TEST_START_ADDRESS (0x80000000)

#define DDR3_TEST_END_ADDRESS   (DDR3_TEST_START_ADDRESS + (4 * 100))
//#define DDR3_TEST_END_ADDRESS   (0xFFFFFFFF)

int ddr3_memory_test()
{
    unsigned int index, value;

    //GEL_TextOut( "DDR3 memory test... Started\n" );
    puts( "DDR3 memory test... Started\n" );

    /* Write a pattern */
    for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4)
    {
       // *index = index;
       *(Uint32 *)index = index;
    }

    /* Read and check the pattern */
    for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4)
    {

        //value = *index;
    	value = *(Uint32 *)index ;

        if (value  != index)
        {
            //GEL_TextOut( "DDR3 memory test... Failed\n" );
        	puts( "DDR3 memory test... Failed\n" );
            return -1;
        }
    }

    /* Write a pattern for complementary values */
    for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4)
    {
        //*index = ~index;
    	*(Uint32 *)index = ~index;
    }

    /* Read and check the pattern */
    for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4)
    {

       // value = *index;
    	value = *(Uint32 *)index;

        if (value  != ~index) {
            //GEL_TextOut( "DDR3 memory test... Failed\n" );
            puts( "DDR3 memory test... Failed\n" );
            return -1;
        }
    }

    //GEL_TextOut( "DDR3 memory test... Passed\n" );
    puts( "DDR3 memory test... Passed\n" );
    return 0;
}