C6657 RBL boot with DDR3

1、For C6657 device, the DDR PLL initialization sequence was chnaged after the bootROM code was finalized and also BootROM doesn`t support many features like DDR hardware leveling, etc so our recommendation for user who want to load code in DDR is to setup a lower DDR clock using boot ROM and boot the device and then increase the DDR clock when the application boots up.
e2e.ti.com/.../493269
2、查一下6657 SDK tiboot_c665x.h文件,里面bootEmif4Tbl_s有对DDR configuration table的解释.
3、哪个文档？

1. tiboot_c665x.h头文件中对DDR的描述
typedef struct bootEmif4Tbl_s {
UINT32 configSelect_msw; /* Bit map defining which registers to set */
UINT32 configSelect_slsw; /* Bit map defining which registers to set */
UINT32 configSelect_lsw; /* Bit map defining which registers to set */

UINT32 pllPrediv; /* Values of all 0s will disable the pll */
UINT32 pllMult;
UINT32 pllPostDiv;

UINT32 sdRamConfig; /* Controlled by bit 1 of configSelect_msw */
UINT32 sdRamConfig2; /* Bit 2 */
UINT32 sdRamRefreshCtl; /* Bit 3 */
UINT32 sdRamTiming1; /* Bit 4 */
UINT32 sdRamTiming2; /* Bit 5 */
UINT32 sdRamTiming3; /* Bit 6 */
UINT32 lpDdrNvmTiming; /* Bit 7 */
UINT32 powerManageCtl; /* Bit 8 */
UINT32 iODFTTestLogic; /* Bit 9 */
UINT32 performCountCfg; /* Bit 10 */
UINT32 performCountMstRegSel; /* Bit 11 */
UINT32 readIdleCtl; /* Bit 12 */
UINT32 sysVbusmIntEnSet; /* Bit 13 */
UINT32 sdRamOutImpdedCalCfg; /* Bit 14 */
UINT32 tempAlterCfg; /* Bit 15 */
UINT32 ddrPhyCtl1; /* Bit 16 */
UINT32 ddrPhyCtl2; /* Bit 17 */
UINT32 priClassSvceMap; /* Bit 18 */
UINT32 mstId2ClsSvce1Map; /* Bit 19 */
UINT32 mstId2ClsSvce2Map; /* Bit 20 */
UINT32 eccCtl; /* Bit 21 */
UINT32 eccRange1; /* Bit 22 */
UINT32 eccRange2; /* Bit 23 */
UINT32 rdWrtExcThresh; /* Bit 24 */

UINT32 chipConfig[64];

} BOOT_EMIF4_TBL_T;

2. 然后我根据这个结构体猜测了一下AddDDRTable的参数含义，
第一行0x00000070 不知道是干嘛的
第二行0x008FFD20 where to load ddr to L2，我没有找到有手册对6657的地址进行说明(6670 6678我找到了)
时钟速率我配置的是156.25*20/3=1041.6666(标准1066,1333,1600)
/*
DDR3 table paramater config
total 120 words
The DDR configuration table location defined by Boot ROM:
C6678: 0x00873500
C6657: 0x008FFD20
*/

0x00, 0x00, 0x00, 0x70, // ???不知道干嘛的
0x00, 0x8F, 0xFD, 0x20, // where to load ddr to L2

0x02, 0x42, 0x80, 0xF5, // config select: Bitmap definig which registers to set
0000 0010 0100 0010 0100 0000 1111 0101 //24bit‬‬猜测0有效

0x00, 0x00, 0x00, 0x00, // pll Prediv--Controlled by bit 1 of configSelect_msw
0x00, 0x00, 0x00, 0x13, // pll mul 156.25*20/3=1041.6666
0x00, 0x00, 0x00, 0x02, // pll post div
0x63, 0x02, 0xAA, 0xB2, //0 sd ram config
0x00, 0x00, 0x00, 0x00, //0 sd ram config2
0x00, 0x00, 0x51, 0x56, //0 sdram fresh cntrl
0x11, 0x13, 0x78, 0x3C, //0 sdram timing 1
0x30, 0x4F, 0x55, 0x23, //0 sdram timing 2
0x55, 0x95, 0x06, 0xAF, //0 sdram timing 3
0x00, 0x00, 0x00, 0x00, //1 lpDdrNvmTiming
0x00, 0x00, 0x00, 0x00, //0 powerManageCtl
0x00, 0x00, 0x00, 0x00, //0 iODFTTestLogic
0x00, 0x01, 0x00, 0x00, //1 oerform count config
0x00, 0x00, 0x00, 0x00, //0 performCountMstRegSel
0x00, 0x00, 0x00, 0x00, //0 readIdleCtl
0x00, 0x00, 0x00, 0x00, //0 sysVbusmIntEnSet
0x70, 0x07, 0x32, 0x14, //0 sdRamoutImppedCalcfg
0x00, 0x00, 0x00, 0x00, //1 tempAlterCfg
0x00, 0x10, 0x01, 0x0F, //0 ddrPhyCtl1
0x00, 0x00, 0x00, 0x00, //0 ddrPhyCtl2
0x00, 0x00, 0x00, 0x00, //1 priClassSvceMap
0x00, 0x00, 0x00, 0x00, //0 mstId2ClsSvce1Map
0x00, 0x00, 0x00, 0x00, //0 mstId2ClsSvce2Map
0x10, 0x00, 0x00, 0x00, //0 ecc cntrl
0x00, 0x00, 0x00, 0x00, //0 eccRange1
0x00, 0x00, 0x00, 0x00, //0 eccRange2
0x00, 0x00, 0x03, 0x05 //0 rdWrtExcThresh

3. 这是我使用的cmd文件，只是将text段挪到DDR3，gel初始化DDR3(no boot)，main函数中没有初始DDR3，debug下程序正常运行。固化SPI加载不得行。
-heap 0x800
-stack 0x1000

//cmd
MEMORY
{
/* Local L2, 0.5~1MB*/
VECTORS: o = 0x10800000 l = 0x00000200
LL2_RW_DATA: o = 0x10800200 l = 0x000DFF00
//DDR_CFG: o = 0x108ffd20 l = 0x180

/* Shared L2 1MB for C6657*/
SL2: o = 0x0C000000 l = 0x001FFFFF

/* External DDR3, upto 2GB per core */
DDR3_CODE: o = 0x80000000 l = 0x01000000 /*set memory protection attribitue as execution only*/
DDR3_R_DATA: o = 0x81000000 l = 0x01000000 /*set memory protection attribitue as read only*/
DDR3_RW_DATA: o = 0x82000000 l = 0x06000000 /*set memory protection attribitue as read/write*/
EMIF16_DATA:o = 0x70000000 l = 0x10000000 /* EMIF16 memory space */
}

SECTIONS
{
vecs > VECTORS

//.emif4Cfg > DDR_CFG
.text> DDR3_RW_DATA
.cinit> SL2
.const> SL2
.switch > SL2

.stack> LL2_RW_DATA
GROUP
{
.neardata
.rodata
.bss
} > LL2_RW_DATA
.far:testBuf > LL2_RW_DATA
.far> LL2_RW_DATA
.fardata > LL2_RW_DATA
.cio> LL2_RW_DATA
.sysmem> LL2_RW_DATA

}