AM5718: SPI传输事件触发EDMA的问题（急）

/*
 * bsp_spi_csl.c
 *
 *  Created on: 2022年3月4日
 *      Author: 
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#include "stdint.h"
#include <stdio.h>
#include <ti/csl/csl_mcspi.h>
#include <ti/csl/csl_i2c.h>
#include <ti/csl/example/utils/uart_console/inc/uartConfig.h>
#include <ti/csl/csl_types.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/csl_edma.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/csl/example/utils/common/inc/app_utils.h>
#include <xdc/runtime/System.h>

/* ========================================================================== */
/*                                 Macros                                     */
/* ========================================================================== */
#define HSI2C_SLAVE_ADDR 0x21
#define SEL_UART3_SPI2   0x0E
#define UART_SEL1_3      0x0C
#define I2C_INT_NUM      56

#define MCSPI_POLLED_MODE      0

#define HSI2C_EN_SPI2      ((uint8_t) 0x40U)
#define HSI2C_ZERO      ((uint8_t) 0x00U)

#define MCSPI_OUT_FREQ              (1000000U)
#define MCSPI_IN_CLK                (48000000U)
#define McSPI_DATA_COUNT            256U // Data Count Transaction

#if (defined (SOC_AM574x) || defined (SOC_AM572x)) || (defined (SOC_AM571x))
#define MCSPI1_BASE_ADDRESS         (CSL_MPU_MCSPI1_REGS)
#define MCSPI2_BASE_ADDRESS         (CSL_MPU_MCSPI2_REGS)
#undef SOC_I2C1_BASE
#define SOC_I2C1_BASE CSL_MPU_I2C1_REGS
#endif
#if defined (SOC_TDA2XX) || defined (SOC_TDA2PX) || defined (SOC_TDA2EX) || defined (SOC_DRA72x) || defined (SOC_DRA75x) || defined (SOC_TDA3XX) || defined (SOC_DRA78x)
#define MCSPI1_BASE_ADDRESS         (SOC_MCSPI1_BASE)
#define MCSPI2_BASE_ADDRESS         (SOC_MCSPI2_BASE)
#endif

/** \brief EDMA3 channel for SPI1 Channel 0 Tx and Rx*/
#define MCSPI1_TX_EVENT                  (34U)
#define MCSPI1_RX_EVENT                  (35U)

/** \brief EDMA3 channel for SPI2 Channel 0 Tx and Rx*/
#define MCSPI2_TX_EVENT                  (42U)
#define MCSPI2_RX_EVENT                  (43U)

/** \brief MCSPI Tx/Rx buffer base address */
#define MCSPI1_TX0_REG                   (SOC_MCSPI1_BASE + (0x138U))
#define MCSPI1_RX0_REG                   (SOC_MCSPI1_BASE + (0x13CU))

#define MCSPI2_TX0_REG                   (SOC_MCSPI2_BASE + (0x138U))
#define MCSPI2_RX0_REG                   (SOC_MCSPI2_BASE + (0x13CU))

/** \brief MCSPI Channel number*/
#define MCSPI_CH_NUM                    (0U)

#define EVT_QUEQUE_NUM                  (0U)
#define DUMMY_CH_NUM                    (5U)

#define EDMA_TDA2XX_U_BASE              CSL_DSP_DSP_EDMA_CC_REGS//(SOC_EDMA_TPCC_BASE_VIRT)

#define EDMA3CC_PaRAM_BASE            (0x4000)
#define EDMA3CC_OPT(n)                (EDMA3CC_PaRAM_BASE + 0x0 + (0x20 * n))

#define EDMA3_CC_XFER_COMPLETION_INT_A15                (12U)
#define EDMA3_CC_XFER_COMPLETION_INT_M4                 (35U)

#define EDMA3_ERROR_INT_A15                              (14)
#define EDMA3_ERROR_INT_A15_1                            (15)
#define EDMA3_ERROR_INT_M4                               (36)
#define EDMA3_ERROR_INT_M4_1                             (37)

#define EDMA3_CC_REGION_A15                             (0U)
#define EDMA3_CC_REGION_M4                              (1U)

#define MCSPI_MASTERSLAVE_POLLED_MODE_TEST   ('1')
#define MCSPI_MASTERSLAVE_DMA_MODE_TEST      ('2')
#define EXIT(opt)                   (('x' == opt) || ('X' == opt))

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */
uint32_t dataToSlave;

uint32_t gChNum = 0;
uint32_t length = 0;
uint8_t dataFromSlave;
uint8_t rxBuffer[McSPI_DATA_COUNT + 10];
uint8_t txBuffer[McSPI_DATA_COUNT + 10];
uint8_t txSlvBuffer[McSPI_DATA_COUNT + 10];
uint8_t rxSlvBuffer[McSPI_DATA_COUNT + 10];

static void (*cb_Fxn[EDMA3_NUM_TCC])(uint32_t tcc, uint32_t status);

volatile uint8_t flagTx = 0;
volatile uint8_t flagRx = 0;
volatile uint8_t flagSlvTx = 0;
volatile uint8_t flagSlvRx = 0;
char gMainMenuOption = MCSPI_MASTERSLAVE_DMA_MODE_TEST;

/*To use UARTConfigPuts function for prints*/
#if defined (SOC_AM574x) || defined (SOC_AM572x) || defined (SOC_AM571x)
uint32_t uartBaseAddr = CSL_MPU_UART1_REGS;
#endif
#if defined (SOC_TDA2XX) || defined (SOC_TDA2PX) || defined (SOC_TDA2EX) || defined (SOC_DRA72x) || defined (SOC_DRA75x)
uint32_t uartBaseAddr = SOC_UART1_BASE;
#endif
#if defined (SOC_TDA3XX) || defined (SOC_DRA78x)
uint32_t uartBaseAddr = SOC_UART1_BASE;
#endif
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
static void McSPI1SetUp(void);
static void McSPI2SetUp(void);
static void McSPIMSTransfer(uint16_t length);
static void McSPIVerifyData(void);
static void McSPIInitializeBuffers(void);
static void sampleDelay(int32_t delay);
static void McSPIMSPolledModeTransfer(uint16_t length);
static void McSPIMasterSlaveAppTest(void);
static void mainMenu(char *option);
static void McSPIConfigureDma(uint32_t length);

static void McSpi1TxEdmaParamSet(uint32_t tccNum, uint32_t chNum,
                                 volatile uint8_t *buffer, uint16_t buffLength);
static void McSpi1RxEdmaParamSet(uint32_t tccNum, uint32_t chNum,
                                 volatile uint8_t *buffer, uint16_t buffLength,
                                 uint32_t destBidxFlag);
static void McSpi2TxEdmaParamSet(uint32_t tccNum, uint32_t chNum,
                                 volatile uint8_t *buffer, uint16_t buffLength);
static void McSpi2RxEdmaParamSet(uint32_t tccNum, uint32_t chNum,
                                 volatile uint8_t *buffer, uint16_t buffLength,
                                 uint32_t destBidxFlag);

static void CallBack_McSPI1(uint32_t tccNum, uint32_t status);
static void CallBack_McSPI2(uint32_t tccNum, uint32_t status);

static void TxDummyPaRAMConfEnable(void);
static void Edma3ErrorHandlerIsr_McSPI1(void *dummy);
static void Edma3ErrorHandlerIsr_McSPI2(void *dummy);

void Edma3ComplHandlerIsr(void *dummy);

static void RequestEDMA3Channels(void);
static void EDMA3IntConfigure(void);
static void EDMA3Initialize(void);

void padConfig_prcmEnable();

void SetupI2C(void);
void SetupI2CTransmit(void);
uint32_t I2CRead();
void configure_board_mux();

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */

static void sampleDelay(int32_t delay)
{
    volatile int32_t i, j;

    for (i = 0; i < delay; i++)
    {
        for (j = 0; j < 100; j++)
            ;
    }
}

int main_spi_csl(void)
{

    while (1)
    {
        mainMenu(&gMainMenuOption);
        if ((MCSPI_MASTERSLAVE_POLLED_MODE_TEST == gMainMenuOption)
                || (MCSPI_MASTERSLAVE_DMA_MODE_TEST == gMainMenuOption))
        {
            System_printf("McSPIMasterSlaveAppTest...\r\n");
            McSPIMasterSlaveAppTest();
        }
        else
        {

            break;
        }
    }

    return 0;
}

static void McSPIMasterSlaveAppTest(void)
{
    if (MCSPI_MASTERSLAVE_POLLED_MODE_TEST == gMainMenuOption)
    {
        System_printf("MCSPI_MASTERSLAVE_POLLED_MODE_TEST...\r\n");
    }
    if (MCSPI_MASTERSLAVE_DMA_MODE_TEST == gMainMenuOption)
    {
        System_printf("MCSPI_MASTERSLAVE_DMA_MODE_TEST...\r\n");
        EDMA3Init(EDMA_TDA2XX_U_BASE, 0);
        System_printf("EDMA3Init success...\r\n");
        /* Initialize the EDMA3 instance.*/
        EDMA3Initialize();
        System_printf("EDMA3Initialize success...\r\n");
        /* Request EDMA3CC for Tx and Rx channels for SPI0. */
        RequestEDMA3Channels();
        System_printf("RequestEDMA3Channels success...\r\n");
    }

    /* Do the necessary set up configurations for McSPI.*/
    McSPI1SetUp();
    System_printf("McSPI1SetUp success...\r\n");

    McSPIInitializeBuffers();
    System_printf("McSPIInitializeBuffers success...\r\n");
    if (MCSPI_MASTERSLAVE_DMA_MODE_TEST == gMainMenuOption)
    {
        McSPIConfigureDma(McSPI_DATA_COUNT);
        System_printf("McSPIConfigureDma success...\r\n");
    }
    McSPIMSTransfer(McSPI_DATA_COUNT);
    System_printf("McSPIMSTransfer success...\r\n");

    /* Verify whether the data written by Master and the one read by
     * Slave are Equal */
    McSPIVerifyData();
    System_printf("McSPIVerifyData success...\r\n");
}

/*
 ** This function will call the necessary McSPI APIs which will configure the
 ** McSPI controller.
 */
static void McSPI1SetUp(void)
{
    uint32_t status = 1U; // FALSE

    /* Reset the McSPI instance.*/
    McSPIReset(MCSPI1_BASE_ADDRESS);

    /* CLOCKACTIVITY bit - OCP and Functional clocks are maintained           */
    /* SIDLEMODE     bit - Ignore the idle request and configure in normal mode
     */
    /* AUTOIDLE      bit - Disable (OCP clock is running free, no gating)     */
    MCSPISysConfigSetup(MCSPI1_BASE_ADDRESS, MCSPI_CLOCKS_OCP_ON_FUNC_ON,
    MCSPI_SIDLEMODE_NO,
                        MCSPI_WAKEUP_DISABLE,
                        MCSPI_AUTOIDLE_OFF);

    /* Enable chip select pin.*/
    McSPICSEnable(MCSPI1_BASE_ADDRESS);

    /* Enable master mode of operation.*/
    McSPIMasterModeEnable(MCSPI1_BASE_ADDRESS);

    /* Perform the necessary configuration for master mode. */
    status = McSPIMasterModeConfig(MCSPI1_BASE_ADDRESS, MCSPI_SINGLE_CH,
    MCSPI_TX_RX_MODE,
                                   MCSPI_DATA_LINE_COMM_MODE_6, gChNum);

    if (0 == status)
    {

    }

    /* Configure the McSPI bus clock depending on clock mode. */
    McSPIClkConfig(MCSPI1_BASE_ADDRESS, MCSPI_IN_CLK, MCSPI_OUT_FREQ, gChNum,
    MCSPI_CLK_MODE_0);

    /* Configure the word length.*/
    McSPIWordLengthSet(MCSPI1_BASE_ADDRESS, MCSPI_WORD_LENGTH(8), gChNum);

    /* Set polarity of SPIEN to low.*/
    McSPICSPolarityConfig(MCSPI1_BASE_ADDRESS, (MCSPI_CH0CONF_EPOL_ACTIVELOW <<
    MCSPI_CH0CONF_EPOL_SHIFT),
                          gChNum);

    /* Enable the transmitter FIFO of McSPI peripheral.*/
    McSPITxFIFOConfig(MCSPI1_BASE_ADDRESS, MCSPI_TX_FIFO_ENABLE, gChNum);

    /* Enable the receiver FIFO of McSPI peripheral.*/
    McSPIRxFIFOConfig(MCSPI1_BASE_ADDRESS, MCSPI_RX_FIFO_ENABLE, gChNum);
}

static void McSPIConfigureDma(uint32_t length)
{
    /* DMA PaRAM Configuration for McSPI1 */
    /* Configure the read data parameters of McSPI for Edma transmit.*/
    McSpi1TxEdmaParamSet(MCSPI1_TX_EVENT, MCSPI1_TX_EVENT, txBuffer, length);

    /* Configure the read data parameters of McSPI for Edma receive.*/
    McSpi1RxEdmaParamSet(MCSPI1_RX_EVENT, MCSPI1_RX_EVENT, rxBuffer, length,
                         TRUE);

    /* Register the call-back function for Tx/Rx edma events of McSPI.*/
    cb_Fxn[MCSPI1_TX_EVENT] = &CallBack_McSPI1;
    cb_Fxn[MCSPI1_RX_EVENT] = &CallBack_McSPI1;

    /* Set the word count field with the data length to be transferred.*/
    McSPIWordCountSet(MCSPI1_BASE_ADDRESS, length);

    /* Enable the Tx/Rx DMA events for McSPI. */
    McSPIDMAEnable(MCSPI1_BASE_ADDRESS,
                   (MCSPI_DMA_RX_EVENT | MCSPI_DMA_TX_EVENT),
                   MCSPI_CH_NUM);
}

static void McSPIInitializeBuffers(void)
{
    uint32_t index = 0;

    for (index = 0; index < McSPI_DATA_COUNT; index++)
    {
        /* Initialize the txBuffer McSPI1 with a known pattern of data */
        txBuffer[index] = (uint8_t) index;
        /* Initialize the rxBuffer McSPI1 with 0 */
        rxBuffer[index] = (uint8_t) 0;
    }
    for (index = 0; index < McSPI_DATA_COUNT; index++)
    {
        /* Initialize the txBuffer McSPI1 with a known pattern of data */
        txSlvBuffer[index] = (uint8_t) index;
        /* Initialize the rxBuffer McSPI1 with 0 */
        rxSlvBuffer[index] = 0;
    }
}

static void McSPIMSTransfer(uint16_t length)
{
    /* Enable the McSPI channel for communication.*/
    McSPIChannelEnable(MCSPI1_BASE_ADDRESS, gChNum);

    /* SPIEN line is forced to low state.*/
    McSPICSAssert(MCSPI1_BASE_ADDRESS, gChNum);
    if (MCSPI_MASTERSLAVE_DMA_MODE_TEST == gMainMenuOption)
    {
        /* For DMA mode wait for EDMA ISR to happen */
        while ((0 == flagTx) || (flagRx == 0) || (0 == flagSlvTx)
                || (flagSlvRx == 0))
            ;
    }
    else
    {

    }

    /* Force SPIEN line to the inactive state.*/
    McSPICSDeAssert(MCSPI1_BASE_ADDRESS, gChNum);

    /* Disable the McSPI channel.*/
    McSPIChannelDisable(MCSPI1_BASE_ADDRESS, gChNum);
}

/*
 ** This function will verify the data written to and read from flash and print
 ** the appropriate message.
 */
static void McSPIVerifyData(void)
{
    uint32_t index = 0;
    uint32_t error = 0;

    for (index = 0; index < McSPI_DATA_COUNT; index++)
    {
        if ((rxSlvBuffer[index] != txBuffer[index])
                || (txSlvBuffer[index] != rxBuffer[index]))
        {

            error = 1;
            break;
        }
    }

    if (error == 0)
    {

    }
}

/*
 ** This function configures the power supply for EDMA3 Channel Controller 0
 ** and Transfer Controller 0, registers the EDMA interrupts in AINTC.
 */
static void EDMA3Initialize(void)
{
    /* Configuring the AINTC to receive EDMA3 Interrupts */
    EDMA3IntConfigure();
}

/*
 ** EDMA3 completion Interrupt Service Routine(ISR).
 */
void Edma3ComplHandlerIsr(void *dummy)
{
    uint32_t pendingIrqs;
    volatile uint32_t isIPR = 0;
    volatile uint32_t isIPRH = 0;

    uint32_t indexl;
    uint32_t Cnt = 0;

    indexl = 1;
    System_printf("Edma3ComplHandlerIsr...\r\n");
    isIPR = EDMA3GetIntrStatus(EDMA_TDA2XX_U_BASE);
    isIPRH = EDMA3IntrStatusHighGet(EDMA_TDA2XX_U_BASE);

    if (isIPR)
    {
        while ((Cnt < EDMA3CC_COMPL_HANDLER_RETRY_COUNT) && (indexl != 0))
        {
            indexl = 0;

            pendingIrqs = EDMA3GetIntrStatus(EDMA_TDA2XX_U_BASE);

            while (pendingIrqs)
            {
                if ((pendingIrqs & 1) == TRUE)
                {
                    /**
                     * If the user has not given any callback function
                     * while requesting the TCC, its TCC specific bit
                     * in the IPR register will NOT be cleared.
                     */
                    /* Here write to ICR to clear the corresponding IPR bits. */
                    EDMA3ClrIntr(EDMA_TDA2XX_U_BASE, indexl);

                    (*cb_Fxn[indexl])(indexl, EDMA3_XFER_COMPLETE);
                }

                ++indexl;

                pendingIrqs >>= 1;
            }
            Cnt++;
        }
    }

    indexl = 32;

    if (isIPRH)
    {
        while ((Cnt < EDMA3CC_COMPL_HANDLER_RETRY_COUNT) && (indexl != 0))
        {
            indexl = 32;

            pendingIrqs = EDMA3IntrStatusHighGet(EDMA_TDA2XX_U_BASE);

            while (pendingIrqs)
            {
                if ((pendingIrqs & 1) == TRUE)
                {
                    /**
                     * If the user has not given any callback function
                     * while requesting the TCC, its TCC specific bit
                     * in the IPR register will NOT be cleared.
                     */
                    /* Here write to ICR to clear the corresponding IPR bits. */
                    EDMA3ClrIntr(EDMA_TDA2XX_U_BASE, indexl);

                    (*cb_Fxn[indexl])(indexl, EDMA3_XFER_COMPLETE);
                }

                ++indexl;

                pendingIrqs >>= 1;
            }
            Cnt++;
        }
    }
}

void Edma3ErrorHandlerIsr(void *dummy)
{
    Edma3ErrorHandlerIsr_McSPI1(dummy);
}
/* EDMA3 Error Handler */
static void Edma3ErrorHandlerIsr_McSPI1(void *dummy)
{
    volatile uint32_t pendingIrqs = 0;
    volatile uint32_t pendingHIrqs = 0;
    uint32_t txEventHighNo = 0;
    uint32_t rxEventHighNo = 0;
    System_printf("Edma3ErrorHandlerIsr_McSPI1...\r\n");
    pendingIrqs = EDMA3GetErrIntrStatus(EDMA_TDA2XX_U_BASE);
    pendingHIrqs = EDMA3ErrIntrHighStatusGet(EDMA_TDA2XX_U_BASE);

    if (pendingIrqs)
    {
        txEventHighNo = MCSPI1_TX_EVENT & 0x1F;
        rxEventHighNo = MCSPI1_RX_EVENT & 0x1F;

        if ((pendingIrqs & (0x01 << txEventHighNo)))
        {
            /* clear the pending error interrupt */
            EDMA3ClrMissEvt(EDMA_TDA2XX_U_BASE, MCSPI1_TX_EVENT);

            /* Disable McSPI Transmit event */
            McSPIDMADisable(MCSPI1_BASE_ADDRESS, MCSPI_CH0CONF_DMAW_MASK,
            MCSPI_CH_NUM);

            /* Disable Edma Transfer */
            EDMA3DisableTransfer(EDMA_TDA2XX_U_BASE, MCSPI1_TX_EVENT,
            EDMA3_TRIG_MODE_EVENT);

            flagTx = 1;
        }
        else if ((pendingIrqs & (0x01 << rxEventHighNo)))
        {
            /* clear the pending error interrupt */
            EDMA3ClrMissEvt(EDMA_TDA2XX_U_BASE, MCSPI1_RX_EVENT);

            /* Disable McSPI Receive event */
            McSPIDMADisable(MCSPI1_BASE_ADDRESS, MCSPI_CH0CONF_DMAR_MASK,
            MCSPI_CH_NUM);

            /* Disable Edma Transfer */
            EDMA3DisableTransfer(EDMA_TDA2XX_U_BASE, MCSPI1_RX_EVENT,
            EDMA3_TRIG_MODE_EVENT);

            flagRx = 1;
        }
    }
    else if (pendingHIrqs)
    {
        txEventHighNo = MCSPI1_TX_EVENT - 32;
        rxEventHighNo = MCSPI1_RX_EVENT - 32;

        if ((pendingHIrqs & (0x01 << txEventHighNo)))
        {
            /* clear the pending error interrupt */
            EDMA3ClrMissEvt(EDMA_TDA2XX_U_BASE, MCSPI1_TX_EVENT);

            /* Disable McSPI Transmit event */
            McSPIDMADisable(MCSPI1_BASE_ADDRESS, MCSPI_CH0CONF_DMAW_MASK,
            MCSPI_CH_NUM);

            /* Disable Edma Transfer */
            EDMA3DisableTransfer(EDMA_TDA2XX_U_BASE, MCSPI1_TX_EVENT,
            EDMA3_TRIG_MODE_EVENT);

            flagTx = 1;
        }
        else if ((pendingIrqs & (0x01 << rxEventHighNo)))
        {
            /* clear the pending error interrupt */
            EDMA3ClrMissEvt(EDMA_TDA2XX_U_BASE, MCSPI1_RX_EVENT);

            /* Disable McSPI Receive event */
            McSPIDMADisable(MCSPI1_BASE_ADDRESS, MCSPI_CH0CONF_DMAR_MASK,
            MCSPI_CH_NUM);

            /* Disable Edma Transfer */
            EDMA3DisableTransfer(EDMA_TDA2XX_U_BASE, MCSPI1_RX_EVENT,
            EDMA3_TRIG_MODE_EVENT);

            flagRx = 1;
        }
    }
    else
    {
        /* Events has to be cross bar mapped */
    }
}

/*
 ** Call back function. Here we disable the Tx/Rx DMA events of McSPI
 ** peripheral.
 */
static void CallBack_McSPI1(uint32_t tccNum, uint32_t status)
{
    if (tccNum == MCSPI1_TX_EVENT)
    {
        flagTx = 1;

        /* Disable McSPI Transmit event */
        McSPIDMADisable(MCSPI1_BASE_ADDRESS, MCSPI_CH0CONF_DMAW_MASK,
        MCSPI_CH_NUM);
    }

    if (tccNum == MCSPI1_RX_EVENT)
    {
        flagRx = 1;

        /* Disable McSPI Receive event */
        McSPIDMADisable(MCSPI1_BASE_ADDRESS, MCSPI_CH0CONF_DMAR_MASK,
        MCSPI_CH_NUM);
    }
}

/*
 ** This function is used to set the PaRAM entries of EDMA3 for the Receive
 ** event of channel 0 of McSPI1 instance. The corresponding EDMA3 channel
 ** is also enabled for reception.
 */
static void McSpi1RxEdmaParamSet(uint32_t tccNum, uint32_t chNum,
                                 volatile uint8_t *buffer, uint16_t buffLength,
                                 uint32_t destBidxFlag)
{
    EDMA3CCPaRAMEntry paramSet = { 0 };

    /* Fill the PaRAM Set with Receive specific information.*/

    /* srcAddr holds address of SPI Rx FIFO.*/
    paramSet.srcAddr = (uint32_t) (MCSPI1_RX0_REG);

    /* destAddr is address of memory location named buffer.*/
    paramSet.destAddr = (uint32_t) buffer;

    /* aCnt holds the number of bytes in an array.*/
    paramSet.aCnt = 1;

    /* bCnt holds the number of such arrays to be transferred.*/
    paramSet.bCnt = buffLength;

    /* cCnt holds the number of frames of aCnt*bBcnt bytes to be transferred.*/
    paramSet.cCnt = 1;

    /* The srcBidx should not be incremented since it is a h/w register.*/
    paramSet.srcBIdx = 0;

    if (TRUE == destBidxFlag)
    {
        /* The destBidx should be incremented for every byte.*/
        paramSet.destBIdx = 1;
    }
    else
    {
        /* The destBidx should not be incremented.*/
        paramSet.destBIdx = 0;
    }

    /* A sync Transfer Mode. */
    /* srCIdx and destCIdx set to zero since ASYNC Mode is used.*/
    paramSet.srcCIdx = 0;
    paramSet.destCIdx = 0;

    /* Linking transfers in EDMA3 are not used.*/
    paramSet.linkAddr = 0xFFFF;

    paramSet.bCntReload = 0;

    paramSet.opt = 0x00000000;

    /* Set TCC field in OPT with the tccNum.*/
    paramSet.opt |= ((tccNum << EDMA_TPCC_OPT_TCC_SHIFT) &
    EDMA_TPCC_OPT_TCC_MASK);

    /* EDMA3 Interrupt is enabled and Intermediate Interrupt Disabled.*/
    paramSet.opt |= (1 << EDMA_TPCC_OPT_TCINTEN_SHIFT);

    /* Now write the PaRam Set to EDMA3.*/
    EDMA3SetPaRAM(EDMA_TDA2XX_U_BASE, chNum, &paramSet);

    /* EDMA3 Transfer is Enabled.*/
    EDMA3EnableTransfer(EDMA_TDA2XX_U_BASE, chNum, EDMA3_TRIG_MODE_EVENT);
}

/*
 ** This function is used to set the PaRAM entries of EDMA3 for the Transmit
 ** Channel 0 of SPI1 instance. The corresponding EDMA3 channel is also enabled
 ** for transmission.
 */
static void McSpi1TxEdmaParamSet(uint32_t tccNum, uint32_t chNum,
                                 volatile uint8_t *buffer, uint16_t buffLength)
{
    EDMA3CCPaRAMEntry paramSet = { 0 };

    /* Fill the PaRAM Set with transfer specific information. */

    /* srcAddr holds address of memory location buffer. */
    paramSet.srcAddr = (uint32_t) buffer;

    /* destAddr holds address of McSPI_TX register. */
    paramSet.destAddr = (uint32_t) (MCSPI1_TX0_REG);

    /* aCnt holds the number of bytes in an array. */
    paramSet.aCnt = 1;

    /* bCnt holds the number of such arrays to be transferred. */
    paramSet.bCnt = buffLength;

    /* cCnt holds the number of frames of aCnt*bBcnt bytes to be transferred. */
    paramSet.cCnt = 1;

    /*
     ** The srcBidx should be incremented by aCnt number of bytes since the
     ** source used here is memory.
     */
    paramSet.srcBIdx = 1;
    paramSet.destBIdx = 0;

    /* Async Transfer Mode is set in OPT.*/
    /* srCIdx and destCIdx set to zero since ASYNC Mode is used. */
    paramSet.srcCIdx = 0;
    paramSet.destCIdx = 0;

    /* Linking transfers in EDMA3 are not used. */
    paramSet.linkAddr = (EDMA3CC_OPT(DUMMY_CH_NUM));
    paramSet.bCntReload = 0;

    paramSet.opt = 0x00000000;

    /* SAM and DAM fields both are set to 0 */

    /* Set TCC field in OPT with the tccNum. */
    paramSet.opt |= ((tccNum << EDMA_TPCC_OPT_TCC_SHIFT) &
    EDMA_TPCC_OPT_TCC_MASK);

    /* EDMA3 Interrupt is enabled and Intermediate Interrupt Disabled.*/
    paramSet.opt |= (1 << EDMA_TPCC_OPT_TCINTEN_SHIFT);

    /* Now write the PaRam Set to EDMA3.*/
    EDMA3SetPaRAM(EDMA_TDA2XX_U_BASE, chNum, &paramSet);

    /* Dummy param set is enabled */
    TxDummyPaRAMConfEnable();

    /* EDMA3 Transfer is Enabled. */
    EDMA3EnableTransfer(EDMA_TDA2XX_U_BASE, chNum, EDMA3_TRIG_MODE_EVENT);
}

/*
 ** This function allocates EDMA3 channels to McSPI0 for trasmisssion and
 ** reception purposes.
 */
static void RequestEDMA3Channels(void)
{
    /* Request DMA Channel and TCC for SPI Transmit*/
    EDMA3RequestChannel(EDMA_TDA2XX_U_BASE, EDMA3_CHANNEL_TYPE_DMA,
    MCSPI1_TX_EVENT,
                        MCSPI1_TX_EVENT, EVT_QUEQUE_NUM);

    /* Request DMA Channel and TCC for SPI Receive*/
    EDMA3RequestChannel(EDMA_TDA2XX_U_BASE, EDMA3_CHANNEL_TYPE_DMA,
    MCSPI1_RX_EVENT,
                        MCSPI1_RX_EVENT, EVT_QUEQUE_NUM);
}

/*
 ** This function configures the AINTC to receive EDMA3 interrupts.
 */
static void EDMA3IntConfigure(void)
{

    /* Initialize DSP interrupt controller and enable interrupts */
//    IntDSPINTCInit();
//    IntGlobalEnable();
//
//    /* Map EDMA events to DSP interrupts */
//    IntRegister(4, Edma3ComplHandlerIsr);
//    IntEventMap(4, SYS_INT_EDMACOMPINT);
//    IntEnable(4);
//
//    IntRegister(5, Edma3ErrorHandlerIsr);
//    IntEventMap(5, SYS_INT_EDMAERRINT);
//    IntEnable(5);

    Error_Block eb;
    Error_init(&eb);
    Hwi_Handle myHwi1 = NULL, myHwi2 = NULL;
    Hwi_Params myhwiParams;
    Hwi_Params_init(&myhwiParams);
    myhwiParams.eventId = 16;
    myHwi1 = Hwi_create(12, Edma3ComplHandlerIsr, &myhwiParams, &eb);
    if (NULL == myHwi1)
    {
        System_printf("Hwi create failed!\n");
    }
    Hwi_enableInterrupt(12);

    myhwiParams.eventId = 27;
    myHwi2 = Hwi_create(13, Edma3ErrorHandlerIsr, &myhwiParams, &eb);
    if (NULL == myHwi2)
    {
        System_printf("Hwi create failed!\n");
    }
    Hwi_enableInterrupt(13);
}

/*
 ** This configures the PaRAM set for the Dummy Transfer.
 */
static void TxDummyPaRAMConfEnable(void)
{
    EDMA3CCPaRAMEntry dummyPaRAMSet;

    EDMA3GetPaRAM(EDMA_TDA2XX_U_BASE, DUMMY_CH_NUM, &dummyPaRAMSet);

    dummyPaRAMSet.aCnt = 1;
    dummyPaRAMSet.bCnt = 0;
    dummyPaRAMSet.cCnt = 0;
    dummyPaRAMSet.srcAddr = 0;
    dummyPaRAMSet.destAddr = 0;
    dummyPaRAMSet.srcBIdx = 0;
    dummyPaRAMSet.destBIdx = 0;
    dummyPaRAMSet.srcCIdx = 0;
    dummyPaRAMSet.destCIdx = 0;
    dummyPaRAMSet.linkAddr = 0xFFFFU;
    dummyPaRAMSet.bCntReload = 0;
    dummyPaRAMSet.opt = 0;

    EDMA3SetPaRAM(EDMA_TDA2XX_U_BASE, DUMMY_CH_NUM, &dummyPaRAMSet);
}

static void mainMenu(char *option)
{
    while (1)
    {

        if ((MCSPI_MASTERSLAVE_POLLED_MODE_TEST == *option)
                || (MCSPI_MASTERSLAVE_DMA_MODE_TEST == *option) || EXIT(*option))
        {
            break;
        }
        else
        {

        }
    }
}
/********************************* End Of File ******************************/

/*
 * Copyright (c) 2017, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 *  ======== rsc_table_dsp.h ========
 *
 *  Define the resource table entries for all DSP cores. This will be
 *  incorporated into corresponding base images, and used by the remoteproc
 *  on the host-side to allocated/reserve resources.
 *
 */

#ifndef _RSC_TABLE_DSP_H_
#define _RSC_TABLE_DSP_H_

#include <ti/ipc/remoteproc/rsc_types.h>

/* DSP Memory Map */
#define L4_DRA7XX_BASE          0x4A000000

#define L4_PERIPHERAL_L4CFG     (L4_DRA7XX_BASE)
#define DSP_PERIPHERAL_L4CFG    0x4A000000

#define L4_PERIPHERAL_L4PER1    0x48000000
#define DSP_PERIPHERAL_L4PER1   0x48000000

#define L4_PERIPHERAL_L4PER2    0x48400000
#define DSP_PERIPHERAL_L4PER2   0x48400000

#define L4_PERIPHERAL_L4PER3    0x48800000
#define DSP_PERIPHERAL_L4PER3   0x48800000

#define L4_PERIPHERAL_L4EMU     0x54000000
#define DSP_PERIPHERAL_L4EMU    0x54000000

#define L3_PERIPHERAL_DMM       0x4E000000
#define DSP_PERIPHERAL_DMM      0x4E000000

#define L3_TILER_MODE_0_1       0x60000000
#define DSP_TILER_MODE_0_1      0x60000000

#define L3_TILER_MODE_2         0x70000000
#define DSP_TILER_MODE_2        0x70000000

#define L3_TILER_MODE_3         0x78000000
#define DSP_TILER_MODE_3        0x78000000

#define DSP_MEM_TEXT            0x95000000
/* Co-locate alongside TILER region for easier flushing */
#define DSP_MEM_IOBUFS          0x80000000
#define DSP_MEM_DATA            0x95100000
#define DSP_MEM_HEAP            0x95200000

#define DSP_MEM_IPC_DATA        0x9F000000
#define DSP_MEM_IPC_VRING       0x99000000
#define DSP_MEM_RPMSG_VRING0    0x99000000
#define DSP_MEM_RPMSG_VRING1    0x99004000
#define DSP_MEM_VRING_BUFS0     0x99040000
#define DSP_MEM_VRING_BUFS1     0x99080000

#define DSP_MEM_IPC_VRING_SIZE  SZ_1M
#define DSP_MEM_IPC_DATA_SIZE   SZ_1M
#define DSP_MEM_TEXT_SIZE       SZ_1M
#define DSP_MEM_DATA_SIZE       SZ_1M
#define DSP_MEM_HEAP_SIZE       (SZ_1M * 3)
#define DSP_MEM_IOBUFS_SIZE     (SZ_1M * 90)

/* NOTE: Make sure this matches what is configured in the linux device tree */
#define DSP_CMEM_IOBUFS 0xA0000000
#define PHYS_CMEM_IOBUFS 0xA0000000
#define DSP_CMEM_IOBUFS_SIZE (SZ_1M * 192)

/*
 * Assign fixed RAM addresses to facilitate a fixed MMU table.
 */

#define VAYU_DSP_1

/* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
#if defined (VAYU_DSP_1)
#define PHYS_MEM_IPC_VRING      0x99000000
#elif defined (VAYU_DSP_2)
#define PHYS_MEM_IPC_VRING      0x9F000000
#endif

/* Need to be identical to that of IPU */
#define PHYS_MEM_IOBUFS         0xBA300000

/*
 * Sizes of the virtqueues (expressed in number of buffers supported,
 * and must be power of 2)
 */
#define DSP_RPMSG_VQ0_SIZE      256
#define DSP_RPMSG_VQ1_SIZE      256

/* flip up bits whose indices represent features we support */
#define RPMSG_DSP_C0_FEATURES         1

struct my_resource_table {
    struct resource_table base;

    UInt32 offset[18];  /* Should match 'num' in actual definition */

    /* rpmsg vdev entry */
    struct fw_rsc_vdev rpmsg_vdev;
    struct fw_rsc_vdev_vring rpmsg_vring0;
    struct fw_rsc_vdev_vring rpmsg_vring1;

    /* text carveout entry */
    struct fw_rsc_carveout text_cout;

    /* data carveout entry */
    struct fw_rsc_carveout data_cout;

    /* heap carveout entry */
    struct fw_rsc_carveout heap_cout;

    /* ipcdata carveout entry */
    struct fw_rsc_carveout ipcdata_cout;

    /* trace entry */
    struct fw_rsc_trace trace;

    /* devmem entry */
    struct fw_rsc_devmem devmem0;

    /* devmem entry */
    struct fw_rsc_devmem devmem1;

    /* devmem entry */
    struct fw_rsc_devmem devmem2;

    /* devmem entry */
    struct fw_rsc_devmem devmem3;

    /* devmem entry */
    struct fw_rsc_devmem devmem4;

    /* devmem entry */
    struct fw_rsc_devmem devmem5;

    /* devmem entry */
    struct fw_rsc_devmem devmem6;

    /* devmem entry */
    struct fw_rsc_devmem devmem7;

    /* devmem entry */
    struct fw_rsc_devmem devmem8;

    /* devmem entry */
    struct fw_rsc_devmem devmem9;

    /* devmem entry */
    struct fw_rsc_devmem devmem10;

    /* devmem entry */
    struct fw_rsc_devmem devmem11;
};

extern char ti_trace_SysMin_Module_State_0_outbuf__A;
#define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A

#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)

struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
    1,      /* we're the first version that implements this */
    18,     /* number of entries in the table */
    0, 0,   /* reserved, must be zero */
    /* offsets to entries */
    {
        offsetof(struct my_resource_table, rpmsg_vdev),
        offsetof(struct my_resource_table, text_cout),
        offsetof(struct my_resource_table, data_cout),
        offsetof(struct my_resource_table, heap_cout),
        offsetof(struct my_resource_table, ipcdata_cout),
        offsetof(struct my_resource_table, trace),
        offsetof(struct my_resource_table, devmem0),
        offsetof(struct my_resource_table, devmem1),
        offsetof(struct my_resource_table, devmem2),
        offsetof(struct my_resource_table, devmem3),
        offsetof(struct my_resource_table, devmem4),
        offsetof(struct my_resource_table, devmem5),
        offsetof(struct my_resource_table, devmem6),
        offsetof(struct my_resource_table, devmem7),
        offsetof(struct my_resource_table, devmem8),
        offsetof(struct my_resource_table, devmem9),
        offsetof(struct my_resource_table, devmem10),
        offsetof(struct my_resource_table, devmem11),
    },

    /* rpmsg vdev entry */
    {
        TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
        RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
        /* no config data */
    },
    /* the two vrings */
    { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
    { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },

    {
        TYPE_CARVEOUT,
        DSP_MEM_TEXT, 0,
        DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_DATA, 0,
        DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_HEAP, 0,
        DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_IPC_DATA, 0,
        DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
    },

    {
        TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
    },

    {
        TYPE_DEVMEM,
        DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
        DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
    },

    {
        TYPE_DEVMEM,
        DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
        DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
        SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_2, L3_TILER_MODE_2,
        SZ_128M, 0, 0, "DSP_TILER_MODE_2",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_3, L3_TILER_MODE_3,
        SZ_128M, 0, 0, "DSP_TILER_MODE_3",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
        SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
        SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
        SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
        SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
        SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
        SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
    },

    {
        TYPE_DEVMEM,
        DSP_CMEM_IOBUFS, PHYS_CMEM_IOBUFS,
        DSP_CMEM_IOBUFS_SIZE, 0, 0, "DSP_CMEM_IOBUFS",
    },
};

#endif /* _RSC_TABLE_DSP_H_ */

/*
 * Copyright (c) 2013-2015, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 *  ======== config.bld ========
 *
 */
var Build = xdc.useModule('xdc.bld.BuildEnvironment');

/*  Memory Map for ti.platforms.evmDRA7XX:dsp1 and ti.platforms.evmDRA7XX:dsp2
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  9500_4000   ????_????    10_0000  (  ~1 MB) EXT_CODE
 *  9510_0000   ????_????    10_0000  (   1 MB) EXT_DATA
 *  9520_0000   ????_????    30_0000  (   3 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapDsp = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x95000000,
        len:  0x00100000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x95100000,
        len:  0x00100000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x95200000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    },
};

Build.platformTable["ti.platforms.evmDRA7XX:dsp1"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapDsp.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapDsp.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapDsp.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapDsp.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapDsp.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapDsp.PM_DATA ],
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};
Build.platformTable["ti.platforms.evmDRA7XX:dsp2"] =
	Build.platformTable["ti.platforms.evmDRA7XX:dsp1"];


/*  Memory Map for ti.platforms.evmDRA7XX:ipu2
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  0000_4000   ????_????    5F_C000  (  ~6 MB) EXT_CODE
 *  8000_0000   ????_????    60_0000  (   6 MB) EXT_DATA
 *  8060_0000   ????_????   960_0000  (  86 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapIpu2 = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x00004000,
        len:  0x005FC000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x80000000,
        len:  0x00600000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x80600000,
        len:  0x09600000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    }
};

Build.platformTable["ti.platforms.evmDRA7XX:ipu2"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapIpu2.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapIpu2.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu2.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu2.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapIpu2.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapIpu2.PM_DATA ]
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};

/*  Memory Map for ti.platforms.evmDRA7XX:ipu1
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  0000_4000   ????_????     F_C000  (  ~1 MB) EXT_CODE
 *  8000_0000   ????_????    20_0000  (   2 MB) EXT_DATA
 *  8020_0000   ????_????    30_0000  (   3 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapIpu1 = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x00004000,
        len:  0x000FC000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x80000000,
        len:  0x00200000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x80200000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    }
};

Build.platformTable["ti.platforms.evmDRA7XX:ipu1"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapIpu1.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapIpu1.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu1.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu1.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapIpu1.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapIpu1.PM_DATA ]
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};

/*
 * Do not modify this file; it is automatically generated from the template
 * linkcmd.xdt in the ti.targets.elf package and will be overwritten.
 */

/*
 * put '"'s around paths because, without this, the linker
 * considers '-' as minus operator, not a file name character.
 */


-l"R:\tmpdesktop\A390_C6000_Project\Debug\configPkg\package\cfg\A390_pe66.oe66"
-l"R:\tmpdesktop\A390_C6000_Project\TiConfig\source\src\ipc\ipc.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\ipc_3_50_04_08\packages\ti\pm\lib\release\ti.pm_null.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\edma3_lld_2_12_05_30E\packages\ti\sdo\edma3\drv\sample\lib\tda2xx-evm\66\release\edma3_lld_drv_sample.ae66"
-l"R:\tmpdesktop\A390_C6000_Project\TiConfig\source\src\utils\utils.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\pdk_am57xx_1_0_18\packages\ti\board\lib\idkAM571x\c66\release\ti.board.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\pdk_am57xx_1_0_18\packages\ti\drv\i2c\lib\c66\release\ti.drv.i2c.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\pdk_am57xx_1_0_18\packages\ti\drv\uart\lib\c66\release\ti.drv.uart.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\pdk_am57xx_1_0_18\packages\ti\drv\gpio\lib\am571x\c66\release\ti.drv.gpio.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\pdk_am57xx_1_0_18\packages\ti\osal\lib\tirtos\c66\release\ti.osal.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\pdk_am57xx_1_0_18\packages\ti\csl\lib\am571x\c66\release\ti.csl.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\ipc_3_50_04_08\packages\ti\deh\lib\release\ti.deh_vayu.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\bios_6_76_03_01\packages\ti\targets\rts6000\lib\ti.targets.rts6000.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\bios_6_76_03_01\packages\ti\targets\rts6000\lib\boot.ae66"
-l"R:\tmpdesktop\A390_C6000_Project\TiConfig\source\src\sysbios\sysbios.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\ipc_3_50_04_08\packages\ti\trace\lib\release\ti.trace.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\edma3_lld_2_12_05_30E\packages\ti\sdo\edma3\drv\lib\66\release\edma3_lld_drv.ae66"
-l"D:\ti\processor_sdk_rtos_am57xx_06_03_02_08\edma3_lld_2_12_05_30E\packages\ti\sdo\edma3\rm\lib\tda2xx-evm\66\release\edma3_lld_rm.ae66"

--retain="*(xdc.meta)"


--args 0x0
-heap  0x0
-stack 0x1000

MEMORY
{
    L2SRAM (RWX) : org = 0x800000, len = 0x48000
    OCMC_RAM1 (RWX) : org = 0x40300000, len = 0x80000
    OCMC_RAM2 (RWX) : org = 0x40400000, len = 0x100000
    OCMC_RAM3 (RWX) : org = 0x40500000, len = 0x100000
    EXT_CODE (RWX) : org = 0x95000000, len = 0x100000
    EXT_DATA (RW) : org = 0x95100000, len = 0x100000
    EXT_HEAP (RW) : org = 0x95200000, len = 0x300000
    TRACE_BUF (RW) : org = 0x9f000000, len = 0x60000
    EXC_DATA (RW) : org = 0x9f060000, len = 0x10000
    PM_DATA (RWX) : org = 0x9f070000, len = 0x20000
}

/*
 * Linker command file contributions from all loaded packages:
 */

/* Content from xdc.services.global (null): */

/* Content from xdc (null): */

/* Content from xdc.corevers (null): */

/* Content from xdc.rov (null): */

/* Content from xdc.shelf (null): */

/* Content from xdc.services.spec (null): */

/* Content from xdc.services.intern.xsr (null): */

/* Content from xdc.services.intern.gen (null): */

/* Content from xdc.services.intern.cmd (null): */

/* Content from xdc.bld (null): */

/* Content from ti.targets (null): */

/* Content from ti.targets.elf (null): */

/* Content from xdc.services.getset (null): */

/* Content from ti.sdo.ipc.family (null): */

/* Content from ti.sdo.edma3.rm (null): */

/* Content from ti.sdo.edma3.drv (null): */

/* Content from ti.catalog.c6000 (null): */

/* Content from ti.catalog (null): */

/* Content from ti.catalog.peripherals.hdvicp2 (null): */

/* Content from xdc.platform (null): */

/* Content from xdc.cfg (null): */

/* Content from ti.catalog.arp32 (null): */

/* Content from ti.catalog.arm.cortexm4 (null): */

/* Content from ti.catalog.arm.cortexa15 (null): */

/* Content from ti.platforms.evmDRA7XX (null): */

/* Content from ti.trace (null): */

/* Content from ti.sysbios.hal (null): */

/* Content from ti.sysbios.interfaces (null): */

/* Content from xdc.runtime (null): */

/* Content from ti.sysbios.knl (null): */

/* Content from ti.sysbios (null): */

/* Content from ti.sysbios.family.c64p (ti/sysbios/family/c64p/linkcmd.xdt): */

/* Content from ti.sysbios.family.c66 (ti/sysbios/family/c66/linkcmd.xdt): */
ti_sysbios_family_c66_Cache_l1dSize = 32768;
ti_sysbios_family_c66_Cache_l1pSize = 32768;
ti_sysbios_family_c66_Cache_l2Size = 0;

/* Content from ti.sysbios.rts (null): */

/* Content from ti.sysbios.rts.ti (ti/sysbios/rts/ti/linkcmd.xdt): */

/* Content from ti.sysbios.family (null): */

/* Content from xdc.rov.runtime (null): */

/* Content from ti.targets.rts6000 (null): */

/* Content from ti.deh (null): */

/* Content from ti.sysbios.timers.dmtimer (null): */

/* Content from ti.sysbios.family.shared.vayu (null): */

/* Content from ti.csl (null): */

/* Content from ti.osal (null): */

/* Content from ti.drv.gpio (null): */

/* Content from ti.drv.uart (null): */

/* Content from ti.drv.i2c (null): */

/* Content from ti.board (null): */

/* Content from ti.sysbios.gates (null): */

/* Content from ti.sysbios.heaps (null): */

/* Content from xdc.runtime.knl (null): */

/* Content from ti.sdo.utils (null): */

/* Content from ti.sdo.ipc.interfaces (null): */

/* Content from ti.sysbios.syncs (null): */

/* Content from ti.sdo.edma3.drv.sample (null): */

/* Content from ti.sysbios.family.c62 (null): */

/* Content from ti.sysbios.xdcruntime (null): */

/* Content from ti.pm (null): */

/* Content from ti.sysbios.utils (null): */

/* Content from ti.ipc.remoteproc (ti/ipc/remoteproc/linkcmd.xdt): */


    /*
     *  Set entry point to the HWI reset vector 0 to automatically satisfy
     *  any alignment constraints for the boot vector.
     */
    -eti_sysbios_family_c64p_Hwi0

    /*
     * We just modified the entry point, so suppress "entry point symbol other
     * than _c_int00 specified" warning.
     */
    --diag_suppress=10063

/* Content from ti.sdo.ipc.family.vayu (null): */

/* Content from ti.sdo.ipc.notifyDrivers (null): */

/* Content from ti.sdo.ipc (ti/sdo/ipc/linkcmd.xdt): */

SECTIONS
{

    ti_sdo_ipc_init: load > EXT_DATA, type = NOINIT
}

/* Content from ti.ipc.ipcmgr (null): */

/* Content from ti.ipc.transports (null): */

/* Content from ti.ipc.rpmsg (null): */

/* Content from ti.ipc.family.vayu (null): */

/* Content from ti.ipc.namesrv (null): */

/* Content from ti.sdo.ipc.heaps (null): */

/* Content from ti.sdo.ipc.gates (null): */

/* Content from configPkg (null): */

/* Content from xdc.services.io (null): */

/* Content from ti.sdo.ipc.family.ti81xx (null): */


/*
 * symbolic aliases for static instance objects
 */
xdc_runtime_Startup__EXECFXN__C = 1;
xdc_runtime_Startup__RESETFXN__C = 1;
xdc_rov_runtime_Mon__checksum = 1;
xdc_rov_runtime_Mon__write = 1;

SECTIONS
{
    .text: load >> EXT_CODE
    .ti.decompress: load > EXT_CODE
    .stack: load > EXT_DATA
    GROUP: load > EXT_DATA
    {
        .bss:
        .neardata:
        .rodata:
    }
    .cinit: load > EXT_DATA
    .pinit: load >> EXT_DATA
    .init_array: load > EXT_DATA
    .const: load >> EXT_DATA
    .data: load >> EXT_DATA
    .fardata: load >> EXT_DATA
    .switch: load >> EXT_DATA
    .sysmem: load > EXT_DATA
    .far: load >> EXT_DATA
    .args: load > EXT_DATA align = 0x4, fill = 0 {_argsize = 0x0; }
    .cio: load >> EXT_DATA
    .ti.handler_table: load > EXT_DATA
    .c6xabi.exidx: load > EXT_DATA
    .c6xabi.extab: load >> EXT_DATA
    .tracebuf: load > TRACE_BUF
    .errorbuf: load > EXC_DATA
    .resource_table: load > 0x95000000, type = NOINIT
    .vecs: load > EXT_CODE
    xdc.meta: load > EXT_DATA, type = COPY

}

/*
 * Copyright (c) 2013-2015, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 *  ======== config.bld ========
 *
 */
var Build = xdc.useModule('xdc.bld.BuildEnvironment');

var evmDRA7XX_L2SRAM = {
        name: "DSPL2SRAM", space: "data", access: "RWX",
        base: 0x40808000, len: 0x40000,
        comment: "sram Memory (256 KB)"
};

/*  Memory Map for ti.platforms.evmDRA7XX:dsp1 and ti.platforms.evmDRA7XX:dsp2
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  9500_4000   ????_????    10_0000  (  ~1 MB) EXT_CODE
 *  9510_0000   ????_????    10_0000  (   1 MB) EXT_DATA
 *  9520_0000   ????_????    30_0000  (   3 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapDsp = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x95000000,
        len:  0x00100000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x95100000,
        len:  0x00100000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x95200000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    },
    DSPL2SRAM: {
        name: evmDRA7XX_L2SRAM.name,
        base: evmDRA7XX_L2SRAM.base,
        len:  evmDRA7XX_L2SRAM.len,
        space: "data",
        access: "RW"
    }
};

Build.platformTable["ti.platforms.evmDRA7XX:dsp1"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapDsp.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapDsp.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapDsp.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapDsp.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapDsp.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapDsp.PM_DATA ],
        [ evmDRA7XX_L2SRAM.name, evmDRA7XX_ExtMemMapDsp.DSPL2SRAM ],
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};
Build.platformTable["ti.platforms.evmDRA7XX:dsp2"] =
	Build.platformTable["ti.platforms.evmDRA7XX:dsp1"];


/*  Memory Map for ti.platforms.evmDRA7XX:ipu2
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  0000_4000   ????_????    5F_C000  (  ~6 MB) EXT_CODE
 *  8000_0000   ????_????    60_0000  (   6 MB) EXT_DATA
 *  8060_0000   ????_????   960_0000  (  86 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapIpu2 = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x00004000,
        len:  0x005FC000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x80000000,
        len:  0x00600000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x80600000,
        len:  0x09600000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    }
};

Build.platformTable["ti.platforms.evmDRA7XX:ipu2"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapIpu2.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapIpu2.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu2.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu2.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapIpu2.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapIpu2.PM_DATA ]
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};

/*  Memory Map for ti.platforms.evmDRA7XX:ipu1
 *
 *  --- External Memory ---
 *  Virtual     Physical        Size            Comment
 *  ------------------------------------------------------------------------
 *  0000_4000   ????_????     F_C000  (  ~1 MB) EXT_CODE
 *  8000_0000   ????_????    20_0000  (   2 MB) EXT_DATA
 *  8020_0000   ????_????    30_0000  (   3 MB) EXT_HEAP
 *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
 *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
 *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
 */
var evmDRA7XX_ExtMemMapIpu1 = {
    EXT_CODE: {
        name: "EXT_CODE",
        base: 0x00004000,
        len:  0x000FC000,
        space: "code",
        access: "RWX"
    },
    EXT_DATA: {
        name: "EXT_DATA",
        base: 0x80000000,
        len:  0x00200000,
        space: "data",
        access: "RW"
    },
    EXT_HEAP: {
        name: "EXT_HEAP",
        base: 0x80200000,
        len:  0x00300000,
        space: "data",
        access: "RW"
    },
    TRACE_BUF: {
        name: "TRACE_BUF",
        base: 0x9F000000,
        len:  0x00060000,
        space: "data",
        access: "RW"
    },
    EXC_DATA: {
        name: "EXC_DATA",
        base: 0x9F060000,
        len:  0x00010000,
        space: "data",
        access: "RW"
    },
    PM_DATA: {
        name: "PM_DATA",
        base: 0x9F070000,
        len:  0x00020000,
        space: "data",
        access: "RWX"  /* should this have execute perm? */
    }
};

Build.platformTable["ti.platforms.evmDRA7XX:ipu1"] = {
    externalMemoryMap: [
        [ "EXT_CODE", evmDRA7XX_ExtMemMapIpu1.EXT_CODE ],
        [ "EXT_DATA", evmDRA7XX_ExtMemMapIpu1.EXT_DATA ],
        [ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu1.EXT_HEAP ],
        [ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu1.TRACE_BUF ],
        [ "EXC_DATA", evmDRA7XX_ExtMemMapIpu1.EXC_DATA ],
        [ "PM_DATA", evmDRA7XX_ExtMemMapIpu1.PM_DATA ]
    ],
    codeMemory: "EXT_CODE",
    dataMemory: "EXT_DATA",
    stackMemory: "EXT_DATA",
};