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本人使用virtex 5 与dsp c6678 srio通信,fpga是从模式,一直使用的1x。现在调试4x的时候遇到问题,4x会自动变成1x通信,或者:dsp成4x,fpga也训练成4x,但是此时两者通信不了,查原因发现fpga srio ip核的 lnk_trdy_n信号不对,但lnk_rrdy_n信号正常,mode-sel正常。
希望得到高人解答。(Serial RapidIO v5.6)
Allen Yin:谢谢你,DSP 4X的配置上没有问题的,
lnk_trdy_n—Indicates 7 consecutive error free control symbols have been received
and 15 consecutive symbols have been sent. The core is fully trained and can now
transmit data. (Link Transmit Ready)
lnk_trdy_n是核的输出信号,当都训练成4x时,唯独这个输出信号不对,所以dsp这边也初始化不了srio。
你最好咨询一下FPGA的厂商关于这个bit出现错误的可能性;
现阶段你可以测试4X的信号质量有没有问题,DSP的SERDES可以调整输出幅度,你可以将它调大一些。
zhanghao
你好,我现在也在做dsp和fpga的srio通讯测试;
我想请问一下,你那边fpga的程序是直接使用的ip核吗,dsp那边那个no loop模式的程序是否需要更改?
因为我现在初始化之后,感觉fpga和dsp并没有建立连接。
你好,谢谢回复!我现在调试66AK2H14和K7之间的SRIO,用到的IP核是SRIOgen2 v3.1,相比于SRIOv5.6有较大修改。DSP这边的程序和Keystone1的相比变化不大。我将DSP作为从端,SRIO每一个链路都能够以5Gbps的速率运行。但是我调试4x的时候,DSP这边就一直报错如下:
Enable Exception handling...
SRIO path configuration 4xLaneABCD
Input port 0 next expected ackID value: 0x0
Output port 0 unacknowledged ackID: 0x0
Output port 0 next transmitted ackID value: 0x0
The output port 0 has encountered a degraded condition. The degraded port error threshold has been reached in the Port n Error Rate Threshold Register.
The output port 0 has encountered (and possibly recovered from) a transmission error. This bit is set when bit 16 is set.
The output port 0 is in the output error-stopped state.
The input port 0 has encountered (and possibly recovered from) a transmission error. This bit is set when bit 8 is set.
The input port 0 is in the input error-stopped state.
The input or output port 0 has encountered an error from which hardware was unable to recover.
Port 0 OK condition. The input and output ports are initialized, and the port is exchanging error-free control symbols with the attached device.
The port 0 detected a delineation error. The port received an unaligned /SC/ or /PD/ or undefined code-group. The capture registers do not have valid information during this error detection.
The port 0 experienced a link timeout. The port did not receive an acknowledge or link-response control symbol within the specified time-out interval. The capture registers do not have valid information during this error detection.
Type of information logged: 0 (0 - packet, 1 - control symbol)
captured error bit in the Port Error Detect Register: 31
control symbol or Bytes 0 to 3 of the packet header that correspond to the error: 0x0
Bytes 4 to 7 of the packet header that corresponds to the error: 0x0
Bytes 8 to 11 of the packet header that corresponds to the error: 0x0
Bytes 12 to 15 of the packet header that corresponds to the error: 0x0
15 8b/10b deconding error have occurred
SP[0]_ERR_STAT = 0x01010102
SP[0]_ERR_DET = 0x00000004
Corrected Error Stop Condition. SP[0]_ERR_STAT = 0x01010102
Clearing Errors.
DSP1 ready as slave for test
不知道你当时具体的问题是什么?是怎么解决的呢?望不吝赐教啊!
input error stopped和output error stopped是SRIO协议定义的错误状态,一般情况下,如果握手信号错误,SRIO硬件能够自动恢复,但是如果出现错误次数较多,SRIO硬件不能修复,就会出现input error 或者out error;
详细的了解见附件SRIO协议手册C.3章节;流程图见Error Recovery;恢复的方法流程中也提到,就是往Port n Control Symbol Transmit 1 寄存器里写 0x2003F044,就能重启握手过程,重启只需要一方发起即可,另一方会自动回应;需要注意的是在握手的过程中如果另一方仍在发送数据包,则有可能不能恢复过来,需要等两边都idle的情况下再重启握手过程。
当然前提是所有的配置都没有问题。
您好,我现在调试也出现这个问题,我们发现是dsp和fpga握手之后4x变成了1x,但是不知道为什么会这样,因为两边都是设置的4x,请问您当时是这吗解决的,方便说一下么?
您好!我现在在调试6678与fpga srio通信,也出现了4X变为1X的情况,在单步调试的时候执行到这句话 CSL_SRIO_SetBootComplete(hSrio, 1);的时候发现改变的,您是怎么解决这个问题的?谢谢