您好！
6678和FPGA通信，现在DSP用的是STK的那个SRIO工程，然后uiDspNum= 1，就是选择运行在DSP1上的程序，NO_LOOPBACK,4x5G,
现在FPGA发送给DSP的数据能正确收到，这个工程，当DSP1工作在no_loopback的时候，应该是将收到的数据再发出去。
问题：请问这个在代码中是怎么实现的？比如怎么修改FPGA 发给DSP的是0x12345678，FPGA发送的时候dest_id是0xB2，FPGA的device id是0xA0,
怎么修改DSP把收到0x12345678发给FPGA时的dest id和地址等信息呢？相关工程代码如下：
else if(SRIO_NO_LOOPBACK==loopback_mode) //test between 2 DSPs
{
/*DSP0 is the master for test, DSP0 DirectIO or send message to DSP1.
DSP1 is the slave for test, it monitor the doorbell and message
interrupt to detect the received data*/
if(0==uiDspNum)
{
SRIO_2DSP_Test();
}
//如果DSP做从件 只需要运行这个部分
else
{
srio_cfg.device_ID_routing_config= dsp1_device_ID_routing_config;
srio_cfg.uiNumDeviceId=
sizeof(dsp1_device_ID_routing_config)/
sizeof(SRIO_Device_ID_Routing_Config);
msg_cfg.message_map = DSP1_message_map;
msg_cfg.uiNumMessageMap=
sizeof(DSP1_message_map)/sizeof(SRIO_RX_Message_Map);
srio_cfg.msg_cfg= &msg_cfg;
serdesLinkSetup.linkSpeed_GHz= SRIO_DEFAULT_TEST_SPEED;
srio_cfg.srio_1x2x4x_path_control= SRIO_PATH_CTL_4xLaneABCD;//SRIO_PATH_CTL_1xLaneA_1xLaneB_1xLaneC_1xLaneD;//SRIO_PATH_CTL_1xLaneA;//SRIO_PATH_CTL_1xLaneA_1xLaneB_1xLaneC_1xLaneD;
srio_identify_used_ports_lanes(srio_cfg.srio_1x2x4x_path_control);
/*On dual Nyquist EVM only lane 2 and 3 are connected between 2 DSPs*/
srio_cfg.blockEn.bLogic_Port_EN[0]= TRUE;
srio_cfg.blockEn.bLogic_Port_EN[1]= TRUE;
srio_cfg.blockEn.bLogic_Port_EN[2]= TRUE;
srio_cfg.blockEn.bLogic_Port_EN[3]= TRUE;
KeyStone_SRIO_Init(&srio_cfg);
SRIO_PktDM_init();
/*accumulation is only used for the 2nd DSP for two DSPs test*/
QMSS_Accumulation_config();
puts("DSP1 ready as slave for test");
while(1);
}
非常感谢！
