[参考译文] TMS320F28069M：ePWM 与模拟比较器的同步

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https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1010665/tms320f28069m-synchronization-of-epwm-with-analog-comparator

器件型号：TMS320F28069M

您好！

我正在研究如何使用 F28069在临界导通模式下控制升压 PFC 转换器。

我正在使用 PWM 模块在 TBCTR =零时将 ePWMA 输出设置为高电平、在 TBCTR = CMPA 时将 ePWMA 输出设置为低电平。在临界导通模式下运行时、我将使用模拟比较器检测电感器电流的过零、并使用 COMPOUT 生成 DCAEVT1.SYNC 并复位 TBCTR、从而立即(理论上)将 ePWMA 设置为高电平。

问题在于、ePWMA 输出仅在 COMPOUT 下降沿之后几纳秒变为高电平(我将高电平配置为同步生成事件)。

使用的代码如下所示：

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    EPwm2Regs.TBPRD                     = maximum_period;               // Set Period
    EPwm2Regs.CMPA.half.CMPA            = maximum_period/2;             // Set 50% duty EPWM2A
    EPwm2Regs.TBPHS.half.TBPHS          = 0;                            // Value loaded into TBCTR after DCAEVT1.sync
    EPwm2Regs.TBCTL.bit.CTRMODE         = TB_COUNT_UP;                  // Asymmetrical mode
    EPwm2Regs.TBCTL.bit.PHSEN           = TB_ENABLE;                    // Enable the reset
    EPwm2Regs.TBCTL.bit.PRDLD           = TB_SHADOW;
    EPwm2Regs.TBCTL.bit.SYNCOSEL        = TB_SYNC_DISABLE;              // Don't sync down-stream module
    EPwm2Regs.TBCTL.bit.CLKDIV          = TB_DIV1;                      // Set time-base clock prescale to one
    EPwm2Regs.TBCTL.bit.HSPCLKDIV       = TB_DIV1;                      // Set time-base clock prescale to one
    EPwm2Regs.CMPCTL.bit.SHDWAMODE      = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.SHDWBMODE      = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADAMODE      = CC_CTR_ZERO;                  // load on CTR=Zero
    EPwm2Regs.CMPCTL.bit.LOADBMODE      = CC_CTR_ZERO;                  // load on CTR=Zero
    EPwm2Regs.AQCTLA.bit.ZRO            = AQ_SET;                       // set actions for EPWM2A
    EPwm2Regs.AQCTLA.bit.CAU            = AQ_CLEAR;
    // Digital Compare
    EALLOW;
    EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT;              // Digital Compare A High Input Select
    EPwm2Regs.TZDCSEL.bit.DCAEVT1       = TZ_DCAH_HI;               // Digital Compare Output A Event 1 Selection: DCAH = high, DCAL = don't care
    EPwm2Regs.DCACTL.bit.EVT1SYNCE      = DC_SYNC_ENABLE;           // DCAEVT1 SYNC, Enable/Disable
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    EPwm2Regs.TBPRD                     = maximum_period;               // Set Period
    EPwm2Regs.CMPA.half.CMPA            = maximum_period/2;             // Set 50% duty EPWM2A
    EPwm2Regs.TBPHS.half.TBPHS          = 0;                            // Value loaded into TBCTR after DCAEVT1.sync
    EPwm2Regs.TBCTL.bit.CTRMODE         = TB_COUNT_UP;                  // Asymmetrical mode
    EPwm2Regs.TBCTL.bit.PHSEN           = TB_ENABLE;                    // Enable the reset
    EPwm2Regs.TBCTL.bit.PRDLD           = TB_SHADOW;
    EPwm2Regs.TBCTL.bit.SYNCOSEL        = TB_SYNC_DISABLE;              // Don't sync down-stream module
    EPwm2Regs.TBCTL.bit.CLKDIV          = TB_DIV1;                      // Set time-base clock prescale to one
    EPwm2Regs.TBCTL.bit.HSPCLKDIV       = TB_DIV1;                      // Set time-base clock prescale to one
    EPwm2Regs.CMPCTL.bit.SHDWAMODE      = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.SHDWBMODE      = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADAMODE      = CC_CTR_ZERO;                  // load on CTR=Zero
    EPwm2Regs.CMPCTL.bit.LOADBMODE      = CC_CTR_ZERO;                  // load on CTR=Zero
    EPwm2Regs.AQCTLA.bit.ZRO            = AQ_SET;                       // set actions for EPWM2A
    EPwm2Regs.AQCTLA.bit.CAU            = AQ_CLEAR;

    // Digital Compare
    EALLOW;
    EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT;              // Digital Compare A High Input Select
    EPwm2Regs.TZDCSEL.bit.DCAEVT1       = TZ_DCAH_HI;               // Digital Compare Output A Event 1 Selection: DCAH = high, DCAL = don't care
    EPwm2Regs.DCACTL.bit.EVT1SYNCE      = DC_SYNC_ENABLE;           // DCAEVT1 SYNC, Enable/Disable
    EPwm2Regs.DCACTL.bit.EVT1SRCSEL     = DC_EVT1;                  // DCAEVT1 Source Signal Select
    EDIS;

下面的两个图像显示、无论 COMPOUT 脉冲的持续时间如何、SYNC 始终在 COMPOUT 的下降沿之后发生。