[参考译文] TMS320F28335：TMS320F28335：ADC 共用不工作

int main(void)
{
    /* System Init */
    InitSysCtrl();

    memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (Uint32)&RamfuncsLoadSize);

    /*Call Flash Initialization to setup flash waitstates
     This function must reside in RAM*/
    InitFlash();    // Call the flash wrapper init function

    DINT;

    /* Specific clock setting for ADC*/
    EALLOW;
    SysCtrlRegs.HISPCP.all = ADC_MODCLK;    // HSPCLK = SYSCLKOUT/ADC_MODCLK
    EDIS;

//    vInitGPIO(); // GPIO Init Definitions

    /* Initialize PIE control registers to their default state.
     The default state is all PIE interrupts disabled and flags
     are cleared.
     This function is found in the DSP2833x_PieCtrl.c file.*/
    InitPieCtrl();

    /*Disable CPU interrupts and clear all CPU interrupt flags*/
    IER = 0x0000;
    IFR = 0x0000;

    /*Initialize the PIE vector table with pointers to the shell Interrupt
     Service Routines (ISR).
     This will populate the entire table, even if the interrupt
     is not used in this example.  This is useful for debug purposes.
     The shell ISR routines are found in DSP2833x_DefaultIsr.c.
     This function is found in DSP2833x_PieVect.c.*/

    InitPieVectTable();

    IER |= M_INT1; // Enable CPU Interrupt 1

    /* All Peripheral Configurations */
    vInitPeriPherals();

    ConfigureADC();

    EINT;          // Enable Global interrupt INTM
    ERTM;          // Enable Global realtime interrupt DBGM

    while(1)
    {
        //read gpio status when uart is off
            vGpio_status();
            vADS7952ReadAllChannels(u16Buffer);
            ReadADCChannels(u16AdcVal);
    }
}


//==================================================================================================================================
void ConfigureADC(void)
{
    int i=0;
    InitAdc();

    EALLOW;

    AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x1;
    AdcRegs.ADCTRL1.bit.ACQ_PS = 0xf;
    AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;        // 1  Cascaded mode
    // Configure maximum number of conversions (16 channels)
     AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 15;  // 16 conversions (0 to 15)

    AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;
    AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1;
    AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2;
    AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3;
    AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4;
    AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5;
    AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6;
    AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7;
//    AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x8;
//    AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x9;
//    AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0x10;
//    AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0x11;
//    AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0x12;
//    AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0x13;
//    AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0x14;
//    AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0x15;

    AdcRegs.ADCTRL1.bit.CONT_RUN = 1;       // Setup continuous run
    for (i=0; i<16; i++)
      {
        u16AdcVal[i] = 0;
      }

    //
        // Start SEQ1
        //
        AdcRegs.ADCTRL2.all = 0x2000;


    // Power up the ADC
//    SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;  // Enable ADC clock
//    AdcRegs.ADCTRL3.bit.ADCPWDN = 1;   // Power up ADC core
//    AdcRegs.ADCTRL3.bit.ADCBGRFDN = 3;     // Power up Bandgap and reference
    DELAY_US(5000);                        // Wait for ADC to stabilize

    // Set ADC clock prescaler
//    AdcRegs.ADCTRL3.bit.ADCCLKPS = 6;  // ADC Clock Prescaler (SYSCLK / 7)

    // Configure max conversions and sequencing
//    AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 15;  // Max conversions = 16 (0 to 15)
//    AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;       // Enable cascading mode (16-step sequence)

    // Configure ADC channel selection
//    AdcRegs.ADCCHSELSEQ1.all = 0x3210;  // ADCINA0-3
//    AdcRegs.ADCCHSELSEQ2.all = 0x7654;  // ADCINA4-7
//    AdcRegs.ADCCHSELSEQ3.all = 0xBA98;  // ADCINB0-3
//    AdcRegs.ADCCHSELSEQ4.all = 0xFEDC;  // ADCINB4-7

    // Configure acquisition window
//    AdcRegs.ADCTRL1.bit.ACQ_PS = 6;  // Acquisition window = 7 ADC clock cycles

    // Software trigger mode
//    AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0;       // Ensure auto-sequencer is not triggered
//    AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0;   // Disable interrupts for sequence

    EDIS;
}

void ReadADCChannels(Uint16 *adcResults)
{
    int i=0;


//            for (i=0; i<3; i++)
            {
                //
                // Wait for interrupt
                //
                while (AdcRegs.ADCST.bit.INT_SEQ1== 0)
                {

                }
                AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
                u16AdcVal[0] = AdcMirror.ADCRESULT0;
                /* ADC buffer */   /* ADC result register */     /* ADC Pin in schematic */
                u16AdcVal[0] = (AdcMirror.ADCRESULT0);      //adc_v_vdc1      - ADCINA0
                u16AdcVal[1] = (AdcMirror.ADCRESULT1);      //lv_tm1p1        - ADCINB0
                u16AdcVal[2] = (AdcMirror.ADCRESULT2);      //adc_v_ir        - ADCINA1
                u16AdcVal[3] = (AdcMirror.ADCRESULT3);      //lv_tm1p2        - ADCINB1
                u16AdcVal[4] = (AdcMirror.ADCRESULT4);      //adc_v_iy        - ADCINA2
                u16AdcVal[5] = (AdcMirror.ADCRESULT5);      //lv_tm2p1        - ADCINB2
                u16AdcVal[6] = (AdcMirror.ADCRESULT6);      //adc_v_ib        - ADCINA3
                u16AdcVal[7] = (AdcMirror.ADCRESULT7);      //lv_tm2p2        - ADCINB3
                u16AdcVal[8] = (AdcMirror.ADCRESULT8);      //adc_v_bkchpr    - ADCINA4
                u16AdcVal[9] = (AdcMirror.ADCRESULT9);      //adc_v_vdc4      - ADCINB4
                u16AdcVal[10] = (AdcMirror.ADCRESULT10);    //adc_i_idc       - ADCINA5
                u16AdcVal[11] = (AdcMirror.ADCRESULT11);    //adc_v_vdc5      - ADCINB5
                u16AdcVal[12] = (AdcMirror.ADCRESULT12);    //adc_v_vdc2      - ADCINA6
                u16AdcVal[13] = (AdcMirror.ADCRESULT13);    //adc_v_spare1    - ADCINB6
                u16AdcVal[14] = (AdcMirror.ADCRESULT14);    //adc_v_vdc3      - ADCINA7
                u16AdcVal[15] = (AdcMirror.ADCRESULT15);    //adc_v_spare2    - ADCINB7


            }

}