[参考译文] MSP430FR5994：ADC_12 RDYIFG 标志问题和不同 ADCMTL 寄存器和 CTADRT ADDRX 位的签名

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//******************************************************************************
//  MSP430FR5x9x Demo - ADC12, Sample A1, AVcc Ref, Set P1.0 if A1 > 0.5*AVcc
//
//   Description: A single sample is made on A1 with reference to AVcc.
//   Software sets ADC12SC to start sample and conversion - ADC12SC
//   automatically cleared at EOC. ADC12 internal oscillator times sample (16x)
//   and conversion. In Mainloop MSP430 waits in LPM0 to save power until ADC12
//   conversion complete, ADC12_ISR will force exit from LPM0 in Mainloop on
//   reti. If A1 > 0.5*AVcc, P1.0 set, else reset. The full, correct handling of
//   and ADC12 interrupt is shown as well.
//
//
//                MSP430FR5994
//             -----------------
//         /|\|              XIN|-
//          | |                 |
//          --|RST          XOUT|-
//            |                 |
//        >---|P1.1/A1      P1.0|-->LED
//
//   William Goh
//   Texas Instruments Inc.
//   October 2015
//   Built with IAR Embedded Workbench V6.30 & Code Composer Studio V6.1
//******************************************************************************
#include <msp430.h>

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;               // Stop WDT

    // GPIO Setup
    P1OUT &= ~BIT0;                         // Clear LED to start
    P1DIR |= BIT0;                          // Set P1.0/LED to output
    P1SEL1 |= BIT2;                         // Configure P1.1 for ADC
    P1SEL0 |= BIT2;


    // Disable the GPIO power-on default high-impedance mode to activate
    // previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;

    // Configure Ref voltage generator
    REFCTL0 |=REFVSEL_3|REFON;
    // Configure ADC12
    ADC12CTL0 = ADC12SHT0_2 | ADC12ON;      // Sampling time, S&H=16, ADC12 on
    ADC12CTL1 = ADC12SHP;                   // Use sampling timer
    ADC12CTL2 |= ADC12RES_2;                // 12-bit conversion results
    ADC12MCTL1|= ADC12INCH_2|ADC12VRSEL_1;              // A1 ADC input select; Vref=AVCC
    ADC12IER0 |= ADC12IE0;                  // Enable ADC conv complete interrupt
    ADC12IER2 |=ADC12RDYIE;
    __enable_interrupt();
    while (1)
    {
        while(!(REFCTL0 & REFGENRDY));          // Wait for reference generator
        __delay_cycles(5000);
        ADC12CTL0 |= ADC12ENC
                  | ADC12SC;    // Start sampling/conversion

        __bis_SR_register(LPM0_bits | GIE); // LPM0, ADC12_ISR will force exit
        __no_operation();                   // For debugger
    }
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = ADC12_B_VECTOR
__interrupt void ADC12_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_B_VECTOR))) ADC12_ISR (void)
#else
#error Compiler not supported!
#endif
{
    switch(__even_in_range(ADC12IV, ADC12IV__ADC12RDYIFG))
    {
        case ADC12IV__NONE:        __no_operation(); break;   // Vector  0:  No interrupt
        case ADC12IV__ADC12OVIFG:  __no_operation(); break;   // Vector  2:  ADC12MEMx Overflow
        case ADC12IV__ADC12TOVIFG: __no_operation(); break;   // Vector  4:  Conversion time overflow
        case ADC12IV__ADC12HIIFG:  __no_operation(); break;   // Vector  6:  ADC12BHI
        case ADC12IV__ADC12LOIFG:  __no_operation(); break;   // Vector  8:  ADC12BLO
        case ADC12IV__ADC12INIFG:  __no_operation(); break;   // Vector 10:  ADC12BIN
        case ADC12IV__ADC12IFG0:            // Vector 12:  ADC12MEM0 Interrupt
            if (ADC12MEM0 >= 0x7ff)         // ADC12MEM0 = A1 > 0.5AVcc?
                P1OUT |= BIT0;              // P1.0 = 1
            else
                P1OUT &= ~BIT0;             // P1.0 = 0
                // Exit from LPM0 and continue executing main
                __bic_SR_register_on_exit(LPM0_bits);
            __no_operation(); break;
        case ADC12IV__ADC12IFG1:   __no_operation(); break;   // Vector 14:  ADC12MEM1
        case ADC12IV__ADC12IFG2:   __no_operation(); break;   // Vector 16:  ADC12MEM2
        case ADC12IV__ADC12IFG3:   __no_operation(); break;   // Vector 18:  ADC12MEM3
        case ADC12IV__ADC12IFG4:   __no_operation(); break;   // Vector 20:  ADC12MEM4
        case ADC12IV__ADC12IFG5:   __no_operation(); break;   // Vector 22:  ADC12MEM5
        case ADC12IV__ADC12IFG6:   __no_operation(); break;   // Vector 24:  ADC12MEM6
        case ADC12IV__ADC12IFG7:   __no_operation(); break;   // Vector 26:  ADC12MEM7
        case ADC12IV__ADC12IFG8:   __no_operation(); break;   // Vector 28:  ADC12MEM8
        case ADC12IV__ADC12IFG9:   __no_operation(); break;   // Vector 30:  ADC12MEM9
        case ADC12IV__ADC12IFG10:  __no_operation(); break;   // Vector 32:  ADC12MEM10
        case ADC12IV__ADC12IFG11:  __no_operation(); break;   // Vector 34:  ADC12MEM11
        case ADC12IV__ADC12IFG12:  __no_operation(); break;   // Vector 36:  ADC12MEM12
        case ADC12IV__ADC12IFG13:  __no_operation(); break;   // Vector 38:  ADC12MEM13
        case ADC12IV__ADC12IFG14:  __no_operation(); break;   // Vector 40:  ADC12MEM14
        case ADC12IV__ADC12IFG15:  __no_operation(); break;   // Vector 42:  ADC12MEM15
        case ADC12IV__ADC12IFG16:  __no_operation(); break;   // Vector 44:  ADC12MEM16
        case ADC12IV__ADC12IFG17:  __no_operation(); break;   // Vector 46:  ADC12MEM17
        case ADC12IV__ADC12IFG18:  __no_operation(); break;   // Vector 48:  ADC12MEM18
        case ADC12IV__ADC12IFG19:  __no_operation(); break;   // Vector 50:  ADC12MEM19
        case ADC12IV__ADC12IFG20:  __no_operation(); break;   // Vector 52:  ADC12MEM20
        case ADC12IV__ADC12IFG21:  __no_operation(); break;   // Vector 54:  ADC12MEM21
        case ADC12IV__ADC12IFG22:  __no_operation(); break;   // Vector 56:  ADC12MEM22
        case ADC12IV__ADC12IFG23:  __no_operation(); break;   // Vector 58:  ADC12MEM23
        case ADC12IV__ADC12IFG24:  __no_operation(); break;   // Vector 60:  ADC12MEM24
        case ADC12IV__ADC12IFG25:  __no_operation(); break;   // Vector 62:  ADC12MEM25
        case ADC12IV__ADC12IFG26:  __no_operation(); break;   // Vector 64:  ADC12MEM26
        case ADC12IV__ADC12IFG27:  __no_operation(); break;   // Vector 66:  ADC12MEM27
        case ADC12IV__ADC12IFG28:  __no_operation(); break;   // Vector 68:  ADC12MEM28
        case ADC12IV__ADC12IFG29:  __no_operation(); break;   // Vector 70:  ADC12MEM29
        case ADC12IV__ADC12IFG30:  __no_operation(); break;   // Vector 72:  ADC12MEM30
        case ADC12IV__ADC12IFG31:  __no_operation(); break;   // Vector 74:  ADC12MEM31
        case ADC12IV__ADC12RDYIFG:
            ADC12CTL0 |= ADC12ENC | ADC12SC;    // Start sampling/conversion
            __no_operation();
            break;   // Vector 76:  ADC12RDY
        default: __no_operation(); break;
    }
}