[参考译文] AM6442：如何实施在 MSRAM 上运行的 Linux 系统引导 R5F CPU 项目

//In ipc_rpmsg_echo.c file 105-112 line
uint32_t gRemoteCoreId[] = {
//    CSL_CORE_ID_R5FSS0_0,
    CSL_CORE_ID_R5FSS0_1,
    CSL_CORE_ID_R5FSS1_0,
    CSL_CORE_ID_R5FSS1_1,
//    CSL_CORE_ID_M4FSS0_0,
    CSL_CORE_ID_MAX /* this value indicates the end of the array */
};

//In ipc_rpmsg_echo.c file 316 line
if( IpcNotify_getSelfCoreId() == CSL_CORE_ID_R5FSS0_1 )

oc_sram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x00 0x70000000 0x00 0x200000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x00 0x70000000 0x200000>;

        //SRAM node allocation -> MSRAM: ORIGIN = 0x70080000 , LENGTH = 0x40000 
		main_r5fss0_core0_msram:r5fss0_core0_msram@80000 {
			reg = <0x80000 0x40000>;
		};  

		atf-sram@1c0000 {
			reg = <0x1c0000 0x20000>;
		};

		dmsc-sram@1e0000 {
			reg = <0x1e0000 0x1c000>;
		};

		sproxy-sram@1fc000 {
			reg = <0x1fc000 0x4000>;
		};
	};

		main_r5fss0_core0: r5f@78000000 {
			compatible = "ti,am64-r5f";
			reg = <0x78000000 0x00010000>,
			      <0x78100000 0x00010000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <121>;
			ti,sci-proc-ids = <0x01 0xff>;
			resets = <&k3_reset 121 1>;
			firmware-name = "am64-main-r5f0_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
			sram = <&main_r5fss0_core0_msram>; //sram node reference
		};

SECTIONS
{
    .vectors  : {
    } > R5F_VECS   , palign(8) 

    GROUP  :   {
    .text.hwi : {
    } palign(8)
    .text.cache : {
    } palign(8)
    .text.mpu : {
    } palign(8)
    .text.boot : {
    } palign(8)
    .text:abort : {
    } palign(8)
    } > MSRAM  


    GROUP  :   {
    .text : {
    } palign(8)
    .rodata : {
    } palign(8)
    } > MSRAM  


    GROUP  :   {
    .data : {
    } palign(8)
    } > MSRAM  


    GROUP  :   {
    .bss : {
    } palign(8)
    RUN_START(__BSS_START)
    RUN_END(__BSS_END)
    .sysmem : {
    } palign(8)
    .stack : {
    } palign(8)
    } > MSRAM  

    GROUP  :   {
    .irqstack : {
        . = . + __IRQ_STACK_SIZE;
    } align(8)
    RUN_START(__IRQ_STACK_START)
    RUN_END(__IRQ_STACK_END)
    .fiqstack : {
        . = . + __FIQ_STACK_SIZE;
    } align(8)
    RUN_START(__FIQ_STACK_START)
    RUN_END(__FIQ_STACK_END)
    .svcstack : {
        . = . + __SVC_STACK_SIZE;
    } align(8)
    RUN_START(__SVC_STACK_START)
    RUN_END(__SVC_STACK_END)
    .abortstack : {
        . = . + __ABORT_STACK_SIZE;
    } align(8)
    RUN_START(__ABORT_STACK_START)
    RUN_END(__ABORT_STACK_END)
    .undefinedstack : {
        . = . + __UNDEFINED_STACK_SIZE;
    } align(8)
    RUN_START(__UNDEFINED_STACK_START)
    RUN_END(__UNDEFINED_STACK_END)
    } > MSRAM  


    GROUP  :   {
    .ARM.exidx : {
    } palign(8)
    .init_array : {
    } palign(8)
    .fini_array : {
    } palign(8)
    } > MSRAM  

    .bss.user_shared_mem (NOLOAD) : {
    } > USER_SHM_MEM    

    .bss.log_shared_mem (NOLOAD) : {
    } > LOG_SHM_MEM    

    .bss.ipc_vring_mem (NOLOAD) : {
    } > RTOS_NORTOS_IPC_SHM_MEM    

    .bss.nocache (NOLOAD) : {
    } > NON_CACHE_MEM    
    
    // Add resource_table
    GROUP  :   {
    .resource_table : {
    } palign(4096)
    } > DDR_0  
}

MEMORY
{
    R5F_VECS   : ORIGIN = 0x0 , LENGTH = 0x40 
    R5F_TCMA   : ORIGIN = 0x40 , LENGTH = 0x7FC0 
    R5F_TCMB0   : ORIGIN = 0x41010000 , LENGTH = 0x8000 
    NON_CACHE_MEM   : ORIGIN = 0x70060000 , LENGTH = 0x8000 
    MSRAM   : ORIGIN = 0x70080000 , LENGTH = 0x40000 
    USER_SHM_MEM   : ORIGIN = 0x701D0000 , LENGTH = 0x80 
    LOG_SHM_MEM   : ORIGIN = 0x701D0080 , LENGTH = 0x3F80 
    RTOS_NORTOS_IPC_SHM_MEM   : ORIGIN = 0x701D4000 , LENGTH = 0xC000 
    FLASH   : ORIGIN = 0x60100000 , LENGTH = 0x80000 
    
    DDR_0   : ORIGIN = 0xA0100000 , LENGTH = 0x1000 // Allocate the DDR area to place the resource table
    DDR_1   : ORIGIN = 0xA0101000 , LENGTH = 0xEFF000 
    LINUX_IPC_SHM_MEM   : ORIGIN = 0xA0000000 , LENGTH = 0x100000 
}