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Can't find a source file at "D:\A0132542\code\Tenor_Driverlib\EXAMPLES\c2000-sfo-library\calibration\hrpwm\sfo_bitfield\f28004x_COFF_Debug/../SFO_v8_fpu_lib_build_c28.c"
Locate the file or edit the source lookup path to include its location.
您好，我看了手册：Enable CLA tasks/interrupts
Set appropriate bits in the interrupt enable register (MIER) to allow the CLA to service interrupts
我程序里边配置了： Cla1Regs.MCTL.bit.IACKE = 1;
Cla1Regs.MIER.all = (M_INT8 | M_INT1);
您说的是这个吗？
//
// Map the ISR to the CLA end-of-task interrupt.
//
Interrupt_register(INT_CLA1_1, cla1Isr1);
//*****************************************************************************
//
//! Registers a function to be called when an interrupt occurs.
//!
//! \param interruptNumber specifies the interrupt in question.
//! \param handler is a pointer to the function to be called.
//!
//! This function is used to specify the handler function to be called when the
//! given interrupt is asserted to the processor. When the interrupt occurs,
//! if it is enabled (via Interrupt_enable()), the handler function will be
//! called in interrupt context. Since the handler function can preempt other
//! code, care must be taken to protect memory or peripherals that are accessed
//! by the handler and other non-handler code.
//!
//! The available \e interruptNumber values are supplied in
//! <tt>inc/hw_ints.h</tt>.
//!
//! \note This function assumes that the PIE has been enabled. See
//! Interrupt_initModule().
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_register(uint32_t interruptNumber, void (*handler)(void))
{
uint32_t address;
//
// Calculate appropriate address for the interrupt number
//
address = (uint32_t)PIEVECTTABLE_BASE +
(((interruptNumber & 0xFFFF0000U) >> 16U) * 2U);
//
// Copy ISR address into PIE table
//
EALLOW;
HWREG(address) = (uint32_t)handler;
EDIS;
}
EALLOW;
#ifdef _FLASH
//
// Copy over code from FLASH to RAM
//
memcpy((uint32_t *)&Cla1ProgRunStart, (uint32_t *)&Cla1ProgLoadStart,
(uint32_t)&Cla1ProgLoadSize);
#endif //_FLASH
//
// Initialize and wait for CLA1ToCPUMsgRAM
//
MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};
//
// Initialize and wait for CPUToCLA1MsgRAM
//
MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};
//
// Select LS4RAM and LS5RAM to be the programming space for the CLA
// First configure the CLA to be the master for LS4 and LS5 and then
// set the space to be a program block
//
MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 1;
MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0;
//MemCfgRegs.LSxMSEL.bit.MSEL_LS3 = 1;
//MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS3 = 0;
EDIS;
}
EALLOW;
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_PRD; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // 使能Enable INT,外设级中断允许
EPwm3Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1rd event用于ADC采样转换和CLA=120K
//EPwm3Regs.ETPS.bit.INTPSSEL=1;
//EPwm3Regs.ETINTPS.bit.INTPRD2=1;
