Other Parts Discussed in Thread: MSP430F5529
各位先進好
F5419A 有4個UART PORT.
使用XT2 (8MHZ) 做為CLOCK SOURCE.
單獨使用 UART0.UART2,UART3通訊115200bps 都正常
一旦啟用UART1, 全部UART失效.
且 P11.2 輸出從8MHZ 變1MHZ?
請問 先進 是否有建議 ????
Other Parts Discussed in Thread: MSP430F5529
各位先進好
F5419A 有4個UART PORT.
使用XT2 (8MHZ) 做為CLOCK SOURCE.
單獨使用 UART0.UART2,UART3通訊115200bps 都正常
一旦啟用UART1, 全部UART失效.
且 P11.2 輸出從8MHZ 變1MHZ?
請問 先進 是否有建議 ????
请问您现在情况怎么样了？
我在MSP430F5529 LAUNCHPAD上测试了一下，使用XT2 4Mhz/UART1是可以正常使用的
代码如下
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//******************************************************************************
// MSP430F552x Demo - XT2 sources MCLK & SMCLK
//
// Description: This program demonstrates using XT2 to source MCLK. XT1 is not
// connected in this case.
//
// By default, LFXT1 is requested by the following modules:
// - FLL
// - ACLK
// If LFXT1 is NOT used and if the user does not change the source modules,
// it causes the XT1xxOFIFG flag to be set because it is constantly looking
// for LFXT1. OFIFG, global oscillator fault flag, will always be set if LFXT1
// is set. Hence, it is important to ensure LFXT1 is no longer being sourced
// if LFXT1 is NOT used.
// MCLK = XT2
//
// MSP430F552x
// -----------------
// /|\ | |
// | | |
// ---|RST |
// | XT2IN|-
// | | HF XTAL (455kHz - 16MHz)
// | XT2OUT|-
// | |
// | P7.7|--> MCLK = XT2
// | P2.2|--> SMCLK = XT2
//
// Bhargavi Nisarga
// Texas Instruments Inc.
// April 2009
// Built with CCSv4 and IAR Embedded Workbench Version: 4.21
//******************************************************************************
#include <msp430.h>
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
P2DIR |= BIT2; // SMCLK set out to pins
P2SEL |= BIT2;
P7DIR |= BIT7; // MCLK set out to pins
P7SEL |= BIT7;
P5SEL |= BIT2+BIT3; // Port select XT2
UCSCTL6 &= ~XT2OFF; // Enable XT2
UCSCTL3 |= SELREF_2; // FLLref = REFO
// Since LFXT1 is not used,
// sourcing FLL with LFXT1 can cause
// XT1OFFG flag to set
UCSCTL4 |= SELA_2; // ACLK=REFO,SMCLK=DCO,MCLK=DCO
// Loop until XT1,XT2 & DCO stabilizes - in this case loop until XT2 settles
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
UCSCTL6 &= ~XT2DRIVE0; // Decrease XT2 Drive according to
// expected frequency
UCSCTL4 |= SELS_5 + SELM_5; // SMCLK=MCLK=XT2
//UART
P4SEL |= BIT4+BIT5; // P4.5 = RXD, P4.4=TXD
UCA1CTL1 |= UCSWRST; // **Put state machine in reset**
UCA1CTL1 |= UCSSEL_2; // SMCLK
UCA1BR0 = 34; // 4MHz 115200 (see User's Guide)
UCA1BR1 = 0; // 4MHz 115200
UCA1MCTL |= UCBRS_1 + UCBRF_0; // Modulation UCBRSx=1, UCBRFx=0
UCA1CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA1IE |= UCRXIE; // Enable USCI_A0 RX interrupt
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, interrupts enabled
//while(1); // Loop in place
}
// Echo back RXed character, confirm TX buffer is ready first
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A1_VECTOR
__interrupt void USCI_A1_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_A1_VECTOR))) USCI_A1_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCA1IV,4))
{
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCA1IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
UCA1TXBUF = UCA1RXBUF; // TX -> RXed character
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}