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大家好、
客户有问题需要您的帮助:
原始代码内容:
//############################################################################# // // FILE: ipc_ex2_msgqueue_cm.c // // TITLE: IPC example with interrupt and message queue // //! \addtogroup driver_cm_c28x_dual_example_list //! <h1> IPC message passing example with interrupt and message queue </h1> //! //! This example demonstrates how to configure IPC and pass information from //! C28x to CM core with message queues. //! It is recommended to run the C28x1 core first, followed by the CM core. //! //! \b External \b Connections \n //! - None. //! //! \b Watch \b Variables \n //! - None. //! // //############################################################################# // $Copyright: // Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### // // Included Files // #include "cm.h" #include "ipc.h" // // Defines // #define IPC_CMD_READ_MEM 0x1001 #define IPC_CMD_RESP 0x2001 #define TEST_PASS 0x5555 #define TEST_FAIL 0xAAAA IPC_MessageQueue_t messageQueue; #pragma DATA_SECTION(CMData, "MSGRAM_CM_TO_CPU1") uint32_t CMData[10]; // // IPC ISR for Flag 1 // C28x core sends data with message queue using Flag 0 // __interrupt void IPC_ISR1() { int i; IPC_Message_t TxMsg, RxMsg; bool status = false; // // Read the message from the message queue // IPC_readMessageFromQueue(IPC_CM_L_CPU1_R, &messageQueue, IPC_ADDR_CORRECTION_ENABLE, &RxMsg, IPC_NONBLOCKING_CALL); if(RxMsg.command == IPC_CMD_READ_MEM) { status = true; // // Read and compare data // for(i=0; i<RxMsg.dataw1; i++) { if((*(uint32_t *)RxMsg.address + i) != i) status = false; } } // // Send response message // TxMsg.command = IPC_CMD_RESP; TxMsg.address = (uint32_t)CMData; TxMsg.dataw1 = 10; TxMsg.dataw2 = 1; IPC_sendMessageToQueue(IPC_CM_L_CPU1_R, &messageQueue, IPC_ADDR_CORRECTION_ENABLE, &TxMsg, IPC_NONBLOCKING_CALL); // // Acknowledge the flag // IPC_ackFlagRtoL(IPC_CM_L_CPU1_R, IPC_FLAG1); } // // Main // void main(void) { // // Initialize device clock and peripherals // CM_init(); // // Clear any IPC flags if set already // IPC_clearFlagLtoR(IPC_CM_L_CPU1_R, IPC_FLAG_ALL); // // Enable IPC interrupts // IPC_registerInterrupt(IPC_CM_L_CPU1_R, IPC_INT1, IPC_ISR1); // // Initialize message queue // IPC_initMessageQueue(IPC_CM_L_CPU1_R, &messageQueue, IPC_INT1, IPC_INT1); // // Synchronize both the cores. // IPC_sync(IPC_CM_L_CPU1_R, IPC_FLAG31); int i; for(i=0; i<10; i++) { CMData[i] = i+11; } // // Loop forever. Wait for IPC interrupt // while(1); } // // End of File //
//############################################################################# // // FILE: ipc_ex2_msgqueue_c28x1.c // // TITLE: IPC example with interrupt and message queue // //! \addtogroup driver_cm_c28x_dual_example_list //! <h1> IPC message passing example with interrupt and message queue </h1> //! //! This example demonstrates how to configure IPC and pass information from //! C28x to CM core with message queues. //! It is recommended to run the C28x1 core first, followed by the CM core. //! //! \b External \b Connections \n //! - None. //! //! \b Watch \b Variables \n //! - pass //! // //############################################################################# // $Copyright: // Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### // // Included Files // #include "driverlib.h" #include "device.h" // // Defines // #define IPC_CMD_READ_MEM 0x1001 #define IPC_CMD_RESP 0x2001 #define TEST_PASS 0x5555 #define TEST_FAIL 0xAAAA #pragma DATA_SECTION(CPU1Data, "MSGRAM_CPU_TO_CM") uint32_t CPU1Data[10]; IPC_MessageQueue_t messageQueue; IPC_Message_t TxMsg, RxMsg; uint32_t pass; __interrupt void IPC_ISR1() { int i; bool status = false; // // Read the message from the message queue // IPC_readMessageFromQueue(IPC_CPU1_L_CM_R, &messageQueue, IPC_ADDR_CORRECTION_ENABLE, &RxMsg, IPC_NONBLOCKING_CALL); if(RxMsg.command == IPC_CMD_RESP) { status = true; for(i=0; i<RxMsg.dataw1; i++) { if((*(uint32_t *)RxMsg.address + i) != i+11) status = false; } } // // Send response message // TxMsg.command = IPC_CMD_READ_MEM; TxMsg.address = (uint32_t)CPU1Data; TxMsg.dataw1 = 10; // Using dataw1 as data length TxMsg.dataw2 = 1; // Message identifier IPC_sendMessageToQueue(IPC_CPU1_L_CM_R, &messageQueue, IPC_ADDR_CORRECTION_ENABLE, &TxMsg, IPC_NONBLOCKING_CALL); // // Acknowledge the flag // IPC_ackFlagRtoL(IPC_CPU1_L_CM_R, IPC_FLAG1); Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP11); } // // Main // void main(void) { int i; // // Initialize device clock and peripherals // Device_init(); // // Boot CM core // #ifdef _FLASH Device_bootCM(BOOTMODE_BOOT_TO_FLASH_SECTOR0); #else Device_bootCM(BOOTMODE_BOOT_TO_S0RAM); #endif // // Initialize PIE and clear PIE registers. Disables CPU interrupts. // Interrupt_initModule(); // // Initialize the PIE vector table with pointers to the shell Interrupt // Service Routines (ISR). // Interrupt_initVectorTable(); // // Clear any IPC flags if set already // IPC_clearFlagLtoR(IPC_CPU1_L_CM_R, IPC_FLAG_ALL); // // Enable IPC interrupts // IPC_registerInterrupt(IPC_CPU1_L_CM_R, IPC_INT1, IPC_ISR1); // // Initialize message queue // IPC_initMessageQueue(IPC_CPU1_L_CM_R, &messageQueue, IPC_INT1, IPC_INT1); // // Synchronize both the cores // IPC_sync(IPC_CPU1_L_CM_R, IPC_FLAG31); // // Enable Global Interrupt (INTM) and realtime interrupt (DBGM) // EINT; ERTM; // // Fill in the data to be sent // for(i=0; i<10; i++) { CPU1Data[i] = i; } // // Update the message // TxMsg.command = IPC_CMD_READ_MEM; TxMsg.address = (uint32_t)CPU1Data; TxMsg.dataw1 = 10; // Using dataw1 as data length TxMsg.dataw2 = 1; // Message identifier // // Send message to the queue // Since C28x and CM does not share the same address space for shared RAM, // ADDRESS_CORRECTION is enabled // IPC_sendMessageToQueue(IPC_CPU1_L_CM_R, &messageQueue, IPC_ADDR_CORRECTION_ENABLE, &TxMsg, IPC_NONBLOCKING_CALL); // // End of example. Loop forever // while(1); } // // End of File //
修改:
1.在 CM4内核的 while 循环中、我一直向 CPU1发送消息、但发现 CPU1不能重复进入中断。 原因是什么?
ipc_ex2_msgqueue_cm.c
// // End of example. Loop forever // while(1) { // // Send response message // TxMsg.command = IPC_CMD_RESP; TxMsg.address = (uint32_t)CMData; TxMsg.dataw1 = 10; TxMsg.dataw2 = 1; IPC_sendMessageToQueue(IPC_CM_L_CPU1_R, &messageQueue, IPC_ADDR_CORRECTION_ENABLE, &TxMsg, IPC_NONBLOCKING_CALL); }
2.我想问一下如何理解消息队列的阻塞和非阻塞方法? 也就是说、 根据要选择的情况、我不理解 IPC_nONBLOCKING_CALL 和 IPC_BLOCKING_CALL 这两种方式?
谢谢。此致、
本
您好!
ISR 是否触发一次、而不是再次触发? 我将在明天尝试提供有关 IPC Message Queue 工作方式的更多信息。
此致、
本·科利尔
尊敬的 Benjamin:
有任何更新吗?
此致、
本
Ben、您好!
本杰明目前不在办公室,但他应该能够在下周星期三之前回复你。 很抱歉耽误你的时间。
此致、
阿米尔·奥马尔
尊敬的 Ben:
很抱歉耽误你的时间。 您是否能够确认 客户是否能够至少进入 ISR 一次?
关于'block '参数,我认为最好的理解是 在 ipc.c 中阅读 IPC_sendMessageToQueue()和 IPC_readMessageFromQueue()函数:
如果 Put 缓冲区已满,这看起来像非阻塞调用会使 IPC_sendMessageToQueue()函数立即失败。 blocking 参数将使函数等待、直到 Put 缓冲区槽空闲。
我认为这在实践中意味着 如果没有 IPC_readMessageFromQueue(),IPC_sendMessageToQueue()就不能多次使用 ,否则队列将被填满。 阻塞呼叫将等待(可能永远)队列有空间、而非阻塞呼叫将在队列已满时立即失败。
此致、
本·科利尔
尊敬的 Benjamin:
感谢您的回复!
您 是否能够确认客户是否能够至少输入一次 ISR? [/报价]可以、但只能进入第一个 ISR。
此致、
本
Ben、
在 ISR 已经被触发一次之后、客户是否能够在他们的内存浏览器中检查针对 CM 消息队列的 Put 缓冲区的内容? 此外,他们是否能够进入他们的 IPC_sendMessageToQueue()函数来查看函数内部的情况? 它们是否使其通过了上面的屏幕截图中的 while 循环? 函数第一次运行和后续运行之间是否有任何不同?
此致、
本·科利尔
尊敬的 Benjamin:
现在、我只执行 cm 来发送 IPC 消息、使用 CPU1中断来读取消息、通过将两个内核上的点断开来查看 writeIndex 和 readIndex。
验证过程:
1. CM 首次执行 IPC_sendMessageToQueue()函数后,CPU1进入 IPC 中断,但不进入 IPC_readMessageToQueue()。
如以上两幅图所示、cm 的 PutWriteIndex 和 CPU1的 GetWriteIndex 均为 add 1。
2.在 CM 首次执行 IPC_sendMessageToQueue()函数后,CPU1进入 IPC 中断并 执行 IPC_readMessageToQueue()。
当 CPU1执行 IPC_readMessageToQueue()时, CM 的 PutReadIndex 和 CPU1的 GetReadIndex 都将递增1
根据上述两个验证结果可以重复执行 IPC 的消息队列、代码没有问题。
我以前无法重复该中断的原因是、我仅在 CPU1的 IPC 中断中设置了一个断点、而 CM 没有设置断点、这会导致 CM 继续发送 IPC 消息。 在 PutBuffer 已满并在 IPC_sendMessageToQueue()函数的 while 循环中执行之前,CPU1未进行读取,因此 CPU1无法重复输入中断来读取消息。
对于阻塞呼叫和非阻塞呼叫、如果发送方使用阻塞呼叫持续发送数据、而接收方使用阻塞接收、当发送方的 PutBuffer 已满时、发送方和接收方将进入 while 循环、导致两者工作不正常、 如果其中一个端使用非阻塞调用,则该端可以继续执行其他任务。 我的理解是否正确?
此致、
本
尊敬的 Ben:
您的理解是正确的。 如果您有任何其他问题、请告诉我。
此致、
本·科利尔