SCLK problem using MSP430F2132IPW

Andy Lynn

in this product a TI MICRO (Mfgr part#: MSP430F2132IRHBR; HW part# 300-02087LF) is used that I am using on my prototype as well. Actually my part is not a QFN package but is rather a TSOP package (Mfgr part #: MSP430F2132IPW; HW part# 300-05158), other than that the two TI MICROs are similar.

Via debugger I noticed that a problem using this MICRO wherein I am unable to set the SMCLK from the external XTAL of about 4.9MHz (LFXT1). The MCLK seems to be running fine though.

SMCLK is configured to clock the timers and since SMCLK is unable to run the timers are not running. I was wondering if you could feedback and/or direct this e-mail to a person who has experience using this MICRO? I am attaching a section of my code to show how my clocks are set-up. I am also in touch with a TI FAE but so far no success on this issue. I look forward to your reply. -Thanks

void main(void)

{

unsigned char k;

//WDTCTL = WDT_ARST_250; // initialize WD Time interval

WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer

//pkat - Via BCSCTL1 set LFXT1 mode to High-frequency mode since XTAL is 4.9MHz

// Also set the ACLK divider to 1

BCSCTL1 |= XTS; // intialize clock registers

//pkat - Via BCSTL2 set MCLK to LFXT1CLK (4.9MHz XTAL) and its divider to 1.

// Also set SMCLK (that feeds the counter) to LFXT1CLK and it's divider to 1

BCSCTL2 |= SELS + SELM1 + SELM0; //pkat

//pkat - Via BCSCTL3 set the XTAL's frequency range (3MHz-16MHz option) &

//specifiy the XCAPx capacitance since XTS=1 (high frequency mode specified in BCSCTL1)

BCSCTL3 |= LFXT1S_2; // pkat set BSCTL3 for 4.9MHz crystal

// while(IFG1 & OFIFG) IFG1 &= ~OFIFG; //pkat Orig code commented out

{

IFG1 &= ~OFIFG; //pkat - Clear OSCFault flag

for (int i=0xFF;i>0;i--); //pkat - give time for flag to set

} while(IFG1 &OFIFG); //pkat OSCFlag fault still set?

//pkat Now that the OSCFault flag is clear it is safe to select MCLK's source next

// BCSCTL2 |= SELS+SELM1+SELM0; //pkat commented out original code

BCSCTL2 |= SELS; // pkat- Set SCLK = LFXT1 (safe) again

BCSCTL2 |= SELM_3; // MCLK = LFXT1 (safe)

14 年多前

0 Jason Guo 14 年多前

TI__Expert 3095 points

BCSCTL2 |= SELS + SELM1 + SELM0; //pkat

please remove the above code and try again.

Alternatively ,you can try the following example code.

if still not work, please check your HW design

msp430x21x2_hfxtal.c

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//******************************************************************************
//  MSP430F21x2 Demo - Basic Clock, MCLK Sourced from HF XTAL
//
//  Description: Proper selection of an external HF XTAL for MCLK is shown by
//  first polling the OSC fault until XTAL is stable - only then is MCLK
//  sourced by LFXT1. MCLK/10 is on P1.1 driven by a software loop taking
//  exactly 10 CPU cycles.
//  ACLK = MCLK = LFXT1 = HF XTAL, SMCLK = default DCO ~1.2MHz
//  //* HF XTAL NOT INSTALLED ON FET *//
//  //* Min Vcc required varies with MCLK frequency - refer to datasheet *//
//
//               MSP430F21x2
//            -----------------
//        /|\|              XIN|-
//         | |                 | HF XTAL (3 � 16MHz crystal or resonator)
//         --|RST          XOUT|-
//           |                 |
//           |             P1.1|-->MCLK/10 = HFXTAL/10
//           |             P2.0|-->ACLK = HFXTAL
//
//  A. Dannenberg
//  Texas Instruments Inc.
//  December 2007
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.41A
//******************************************************************************
#include "msp430x21x2.h"
volatile unsigned int i;
void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  P2DIR |= 0x01;                            // P2.0 = output direction
  P2SEL |= 0x01;                            // P2.0 = ACLK function
  P1DIR |= 0x02;                            // P1.1 = output direction
  BCSCTL1 |= XTS;                           // ACLK = LFXT1 = HF XTAL
  BCSCTL3 |= LFXT1S1;                       // 3 � 16MHz crystal or resonator
  do
  {
    IFG1 &= ~OFIFG;                         // Clear OSCFault flag
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

//******************************************************************************
//  MSP430F21x2 Demo - Basic Clock, MCLK Sourced from HF XTAL
//
//  Description: Proper selection of an external HF XTAL for MCLK is shown by
//  first polling the OSC fault until XTAL is stable - only then is MCLK
//  sourced by LFXT1. MCLK/10 is on P1.1 driven by a software loop taking
//  exactly 10 CPU cycles.
//  ACLK = MCLK = LFXT1 = HF XTAL, SMCLK = default DCO ~1.2MHz
//  //* HF XTAL NOT INSTALLED ON FET *//
//  //* Min Vcc required varies with MCLK frequency - refer to datasheet *//
//
//               MSP430F21x2
//            -----------------
//        /|\|              XIN|-
//         | |                 | HF XTAL (3 � 16MHz crystal or resonator)
//         --|RST          XOUT|-
//           |                 |
//           |             P1.1|-->MCLK/10 = HFXTAL/10
//           |             P2.0|-->ACLK = HFXTAL
//
//  A. Dannenberg
//  Texas Instruments Inc.
//  December 2007
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.41A
//******************************************************************************
#include "msp430x21x2.h"

volatile unsigned int i;

void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT

  P2DIR |= 0x01;                            // P2.0 = output direction
  P2SEL |= 0x01;                            // P2.0 = ACLK function
  P1DIR |= 0x02;                            // P1.1 = output direction

  BCSCTL1 |= XTS;                           // ACLK = LFXT1 = HF XTAL
  BCSCTL3 |= LFXT1S1;                       // 3 � 16MHz crystal or resonator

  do
  {
    IFG1 &= ~OFIFG;                         // Clear OSCFault flag
    for (i = 0xFF; i > 0; i--);             // Time for flag to set
  }
  while (IFG1 & OFIFG);                     // OSCFault flag still set?

  BCSCTL2 |= SELM_3;                        // MCLK = LFXT1 (safe)

  for (;;)                                  // Infinite loop
  {
    P1OUT |= 0x02;                          // P1.1 = 1
    P1OUT &= ~0x02;                         // P1.1 = 0
  }
}

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SCLK problem using MSP430F2132IPW